This article is adapted with permission from Semiconductor Digest Magazine as part of their 2026 Outlook series.
By Doug Lefever, Representative Director and Group CEO, Advantest Corp.
The semiconductor industry is entering a new era in which complexity, cost, and performance pressures converge. Meeting these demands will require unprecedented collaboration across the supply chain. In 2026 and beyond, collaboration will be key to pioneering best-in-class test cells that drive velocity and innovation.
From a market perspective, we see artificial intelligence (AI) continuing to drive significant growth in the semiconductor market, spurring new innovations in advanced packaging, high-bandwidth memory (HBM), thermal control, and optical integration to support the next generation of high-performance GPUs. As these complex challenges combine, testing plays a key role in enabling customers to meet time-to-market and quality requirements.
In the coming year, we anticipate continued advancements in 2.5D/3D packaging to enable higher performance in AI and high-performance computing (HPC) devices. Foundries and OSATs are making significant investments in next-generation packaging technology, such as chip-on-wafer-on-substrate (CoWoS), EMIB, through-silicon vias (TSVs), and co-packaged optics (CPO). HBM and other advanced memory technologies also rely on 3D stacking to offer the high processing speeds needed to fuel AI applications.
The increasingly complex architecture of 2.5D/3D chips presents various challenges during test. For example, heightened density and processing speeds elevate temperatures, increasing the risk of failure after wafer-level and final test. This necessitates specialized test equipment with sophisticated thermal-management capabilities and active thermal control. We foresee a growing need for more testing at the singulated-die level, where more precise thermal control can be achieved to capture failures before stacking and ensure only known-good die are packaged.
In addition to die-level test, customers are looking for more ways to reduce yield loss, especially as the cost of 3D packaged devices rises. In response, test companies are moving more test content to earlier insertions. For example, much of the speed and performance testing that used to be reserved for final test is now being performed at wafer sort or singulated die test to ensure that the die can perform high-performance workloads before they are packaged.
We are also beginning to see system-level test content being combined with other test insertions, ensuring better test coverage throughout the back-end flow. We expect all of these trends in test to continue into 2026 as customers seek ways to reduce yield loss and cut costs, and we look forward to seeing what the year ahead will bring.