Data Management Frontiers: Navigating the Semiconductor Landscape with Joe Addiego of Brave Capital
Joe Addiego is a seasoned operating executive and investor with over 20 years of operating experience in technology. His executive leadership contributed to two successful initial public offerings (IPOs), showcasing his strategic acumen in guiding tech companies through critical growth phases. Joe’s operational expertise spans control systems, real-time operating systems, and software development tools, with expertise in data management, networking, and cybersecurity.
Joe has spent the last 25 years as an investor, nurturing startups and establishing markets for innovative technologies holding prominent roles at In-Q-Tel, Alsop Louie Partners, and Brave Capital. As a lead investor for the real-time database company Aerospike, he addressed the data management industry’s need for guaranteed low latency and low cost of ownership. More recent investments include Crunchy Data, an open-source PostgreSQL company that provides a trusted Postgres implementation for enterprises to use either on premises through Kubernetes, or in the cloud as a managed service.
Crunchy Data recently augmented its cloud implementation to include a next-generation Postgres-native data warehouse, enabling everyone to take advantage of high-performance data analytics without leaving Postgres. Throughout Joe’s career he has succeeded at creating new markets for innovative technologies.
In this episode, we dive deep into how data serves as the foundation of cutting-edge innovations across AI, machine learning, adaptive testing, and cybersecurity. This conversation leads us to a comprehensive look at the evolution of data management—from the early days of punch cards and magnetic tapes to today’s sophisticated database systems and cloud solutions.
Throughout the episode, Joe shares his insights on the transformation brought about by the internet era, which has revolutionized how we store, manage, and leverage data in real time across the globe. We’ll examine how these advancements have fueled the explosion of data volumes and how modern technologies have adapted to handle this surge with unprecedented efficiency and security.
Tune in to “Advantest Talks Semi” for a thought-provoking discussion on the history, current trends, and future of data management within the semiconductor industry, and gain valuable perspectives on navigating the complexities of today’s data-driven world. This episode is essential for anyone interested in the intersection of technology and business strategy, providing a clear understanding of how data continues to drive innovation and success in the high-tech landscape.
Read MoreAdvantest Concludes Successful SEMICON Japan 2024 with Record Booth Attendance
Advantest displayed exceptional leadership at SEMICON Japan 2024, held on December 11-13 at the Tokyo Big Sight. As a result of Japan’s efforts to bolster its domestic semiconductor industry, this year’s event saw a record attendance of over 100,000 people compared to 85,000 attendees in 2023. Advantest’s booth received a record number of over 3,500 visitors, including customers, government officials, media personnel, and financial experts. Advantest conducted six interviews with highly respected media outlets such as DigiTimes and Sangyo Times, garnering significant media attention.
Advantest proudly celebrated its 70th anniversary in 2024, embracing this significant milestone with cherished customers and industry partners under the inspiring theme “Facing the Future Together” at SEMICON Japan.
Our application-based display showcased our solutions for applications like artificial intelligence (AI), high-performance compute (HPC), 5G, and automotive. We featured various new products, such as the PMUX02, Wave Scale RF20ex, XHC32, ACS Gemini, and HA1100 Die Prober, highlighting our expansive portfolio.
As a gold sponsor, Advantest sponsored various aspects of this year’s event, including the APCS (Advanced Packaging and Chiplet Summit), sustainability forum, AI technical forum, and many other events during the show. Additionally, Senior Director/Principal Test Strategist Shinji Fujita presented “Optimization of Test Strategies for Innovative Chiplets for HPC/AI Applications” during the SEMI Technology Symposium (STS).
Thank you to everyone who visited us and contributed to the success of SEMICON Japan 2024!
Advantest Introduces SiConic: Groundbreaking Solution for Automated Silicon Validation
This past February, Advantest unveiled SiConic: a scalable solution for automated silicon validation. Designed to address the increasing complexity of advanced systems-on-chip (SoCs), SiConic enables design verification (DV) and silicon validation (SV) engineers to achieve faster sign-off with unparalleled reliability, efficiency and collaboration. SiConic signals Advantest’s commitment to transforming the R&D process for its customers.
The semiconductor industry is facing unprecedented challenges. Growing SoC design complexity, together with the adoption of 3D packaging and heterogeneous integration, is straining traditional validation workflows. DV and SV teams are under pressure to reduce time-to-market and time-to-quality – even as more devices with more intricate features are being developed within constrictive timelines. Reusing the wealth of verification content developed in pre-silicon would provide an efficiency and quality breakthrough. However, the industry lacks the automated flow and tools to reliably re-use and extend verification tests for silicon validation. SiConic’s ecosystem – including EDA partners such as Cadence, Siemens and Synopsys – overcomes this barrier to reuse, enabling engineering efficiency and accelerated test execution on real silicon.
SiConic Explorer, the platform’s software backbone, offers an automated flow by integrating seamlessly with EDA verification tools based on the Accellera Portable Test and Stimulus Standard (PSS), e.g., the Cadence Perspec System Verifier. In addition, integration with debuggers, such as Lauterbach’s TRACE32 debugging tool, accelerates the bring-up of complex multi-IP test cases.
SiConic Link is the hardware foundation of the SiConic solution on a bench. With its high-speed I/O (HSIO) capability, SiConic Link supports protocols such as PCIe and USB to enable functional validation with high throughput and rich tracing capabilities during test execution. The test instrument provides control interfaces (e.g., JTAG, SPI) and general-purpose I/Os, improves the debugging workflow and provides extensive control and observability of the device in its target board environment.
With SiConic, DV engineers can now leverage familiar pre-silicon techniques, expanding their functional coverage in post-silicon. Similarly, SV engineers benefit from seamless load, set parameters and debug of PSS-based or manually directed content on silicon, thereby enabling rapid and reliable device bring-up and functional characterization. The highly portable solution can be easily scaled for use by distributed global R&D teams collaborating on a complex SoC with diverse IP blocks. SiConic enables confident sign-off decisions through team collaboration and data-driven insights – building trust with customers receiving early samples and expecting reliable ramp and operation during the lifetime of their systems.
Advantest Unveils T5801 Ultra-High-Speed Memory Test System to Power Next-Generation DRAM Devices
Early this year, Advantest announced the T5801 Ultra-High-Speed DRAM Test System. The cutting-edge platform is engineered to support the latest advancements in high-speed memory technologies —including GDDR7, LPDDR6, and DDR6 — critical to meeting the growing demands of artificial intelligence (AI), high-performance computing (HPC), and edge applications.
Increasingly complex, high-speed memory technologies are pushing the boundaries of data center and AI performance. The T5801 is tailored to address this challenge by enabling accurate and efficient mass production testing for the highest-speed memory devices. Featuring an innovative Front-End Unit (FEU) architecture, the system is uniquely equipped to handle the rigorous requirements of next-generation DRAM modules, delivering industry-leading performance of up to 36Gbps PAM3 and 18Gbps NRZ.
The T5801 builds on Advantest’s market leadership in DRAM test solutions, including the proven T5503 series and V93000HSM systems. Its support for PAM3, a first in JEDEC-standard DRAMs, highlights the system’s capacity to handle memory innovations such as GDDR7, which is central to achieving ultra-low latency in all AI environments. Its scalable testing infrastructure enables a seamless transition from engineering R&D to production, offering flexible configurations and full compatibility with existing handlers and interfaces.
Advantest Launches KGD Test Cell for Power Semiconductors
Late last year, Advantest announced an integrated test cell designed to maximize die-level test yields for wide-bandgap (WBG) devices essential to power semiconductors. The Advantest Known Good Die (KGD) Test Cell combines the company’s CREA MT Series power device testers with the new HA1100 die prober.
Demand for power semiconductors continues to grow with the rapid escalation of electric vehicles (EV) and power infrastructure. WBG devices, particularly silicon carbide (SiC) and gallium nitride (GaN), are essential for the design and manufacture of power semiconductors, enabling them to be smaller, faster, and more efficient than silicon-based devices. However, failure screening of WBG devices is challenging, as the probe card, the chuck, and the devices can be damaged due to the devices operating at very high voltage and current.
Essentially serving as a one-stop shop for efficient equipment management, the Advantest KGD test cell solution helps reduce customers’ manufacturing costs. CREA’s proprietary probe card interface (PCI) technology can eliminate damage risk. Even if damage issues occur, Advantest will investigate it with the test cell. Customers can minimize the downtime of the test cell. The HA1100 die prober for the CREA MT Series test systems enables assembly of dies in power modules using only passed (KGD) die, ensuring no failed die find their way into the module. This prevents yield loss at module test, thus reducing the loss of final multi-die assembled power modules.
