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Beyond Black Boxes: Meet AI that Justifies Its Choices
Unlock the secrets of AI innovation with our esteemed guest, Jem Davies, non-executive director at Literal Labs. Jem shares his transition from Arm to Literal Labs, revealing how the revolutionary Tsetlin machine sets new benchmarks in efficiency, power usage, and processing speed.
Jem is a highly experienced business leader and technologist, having previously served 18 years at Arm. He is an engineer and was an Arm Fellow, holding multiple patents on CPU and GPU design. Jem’s career moved into business management and he became a general manager first in Arm’s Media Processing Groups, then the founding general manager of their Machine Learning group. In addition to setting future technology roadmaps, he also worked on several acquisitions leading to building new businesses inside Arm, including the Mali GPU (the world’s #1 shipping GPU) and Arm’s AI processors. Jem left Arm in 2021 and is currently chair of NAG and a non-executive director of Literal Labs, BOW, CamAI, and Cambridge Future Tech.
Explore the crucial role of explainable AI and why it matters more than ever in today’s regulated industries like healthcare and finance. Jem discusses Literal Labs’ Tsetlin Machine, which offers an intuitive audit trail of AI decision-making through propositional logic. This approach is breaking new ground by enhancing model efficiency without compromising on performance. We also tackle the challenge of unbiased training data and how tailored levels of explainability can make AI accessible to everyone, from everyday users to industry experts.
As we gaze into the future of AI, we tackle the pressing issues of bias, energy consumption, and the potential impact of quantum computing. Jem provides insight into how Literal Labs is pioneering tools to promote ethical AI development, mitigate biases, and democratize AI innovation. From practical applications like water leak monitoring to the potential for AI to evolve into a tool of unimaginable uses, we reflect on how the intersection of explainability, energy efficiency, and bias shapes a responsible AI future. Join us for an episode that promises to broaden your understanding of AI’s profound societal impact.
Read MoreAdvantest Completes Another Successful SEMICON West
SEMICON West 2024 took place at the Moscone Center in San Francisco, California, on July 9-11, where Advantest once again made a strong presence. This event marks the 25th anniversary of the V93000, as it was unveiled at SEMICON West in 1999.
This year’s SEMICON West hosted 650 exhibiting companies, a 15% increase over last year and saw a 19% increase in attendance from 2023.
Advantest’s booth attracted 242 visitors—an astonishing 50% more than last year—including 12 VIP customers. The booth featured Advantest’s 70th anniversary and corporate theme videos, as well as ACS RTDI, automotive device test solutions, memory platforms, the HA12000 die-level handler, and the V93000 EXA Scale PSML and XHC32 with RDA sockets and boards. Twelve press meetings were conducted, nearly four times the number Advantest usually conducts.
Our customer hospitality event on Wednesday, July 10, proved to be a success as well, attracting almost 250 attendees, 67% of which were customers or non-Advantest guests. We celebrated Advantest’s 70th anniversary and V93000’s 25th anniversary with special cupcakes.
Advantest had a strong presence at the TestVision Symposium as well, presenting multiple papers and posters:
- Keynote – The Rise of AI-Enhanced Test Engineering: Transforming Challenges into Opportunities by Keith Schaub
- Revolutionizing AI Chip Testing with AI-Driven Solutions by Ira Leventhal
- Chiplet Ecosystem Testability for HVM by Bob Bartlett
- Poster presentations
- DPD (Digital Pre-Distortion) for RF Power Amplifier Test by Yichuan Lu
- Optimizing ATE Test Cell Operation with IoT and Cloud Technologies by Vincent Chu
In addition, Ken Butler represented Advantest in the panel discussion, “A Foundation for a Data Driven Future: How to Define, Adapt, and Adopt Standards to Enable a More Intelligent Test Flow and Seamless Operations.”
Another success from the event is that Advantest’s HA1200 test handler was named one of three finalists for the “Best of West” award, a prestigious award presented by SEMI and Semiconductor Digest each year to recognize innovative new products that significantly advance electronics manufacturing capability.
SEMICON West 2025 will take place in October in Phoenix, Arizona, as the conference begins its new rotation between Phoenix and San Francisco.
Read MoreAdvantest Rolls Out Wave Scale RF20ex: High-Frequency, High-Bandwidth RF IC Test Card for the V93000 EXA Scale Platform
Earlier this month, Advantest unveiled the Wave Scale RF20ex instrument for the V93000 EXA Scale platform. It enables customers to test virtually any type of radio frequency (RF) device using a single instrument. Wave Scale RF20ex takes the innovations of the V93000 Wave Scale RF solution to a new level, providing double the number of RF ports per instrument and offering future-proof frequency and bandwidth coverage with a frequency range of 100MHz to 20GHz and an industry-leading 2GHz bandwidth capability. It is well equipped to address 5G, WiFi-7, ultra-wideband (UWB) and any other current or future standards in RF.
As semiconductors continue to evolve toward higher performance, technology convergence and complexity, a broader and more integrated test solution is needed. The new Wave Scale RF20ex provides a unified, single-card solution for all standard RF applications. For UWB applications, Wave Scale RF20ex on the V93000 platform enables ATE for a new class of devices that are more demanding in their testing requirements in terms of modulation bandwidth and frequency coverage while driving higher levels of multi-site test and lower cost-of-test (CoT).
“Our intent in developing Wave Scale RF20ex is to offer the best-in-class instrument for RF ATE with the best available operational efficiency,” said Ralf Stoffels, executive officer and division manager of Advantest’s V93000 product unit. “This single card improves performance for many applications while simplifying configurations that can cover the entire RF market—with built-in capability to also handle the forthcoming WiFi-8 and 6G device generations.”
Wave Scale RF20ex Key Features
The Wave Scale RF20ex card offers a wealth of features and benefits engineered by Advantest RF test experts, including:
- 64 bi-directional ports per card
- 100MHz – 20GHz coverage on all ports
- 2GHz of instantaneous bandwidth for stimulus and measurement
Advantest Announces Advanced Power Multiplexer for V93000 EXA Scale Test Platform
New PMUX02 Power MUX Features High Switch Density and Expanded Voltage Range to Optimize Test of High-Current Devices
Earlier this month, Advantest announced a new power multiplexer developed specifically for use on the V93000 EXA Scale SoC test platform. The PMUX02 Power MUX offers unprecedented capabilities for multi-site testing of power and analog devices, including battery management system (BMS), automotive, and power management ICs. With 22 switches – nearly double the switch density of its predecessor – and an extended voltage range of ±160 volts (V), PMUX02 will help streamline and reduce cost-of-test for these high-pin-count, mixed-signal devices.
A power mux switches between multiple power sources and instruments to provide uninterrupted power and measurement to devices under test (DUTs). Electric vehicles (EVs) are a key driver behind the need for advanced power muxes. Increasing the number of cells stacked in an EV’s battery module improves its efficiency, and stacks of 24+ cells require the BMS to operate at 150V or higher. Moreover, as automotive ICs become increasingly complex with higher pin counts, more parallel sites are required to increase throughput, requiring more multiplexers. PMUX02 provides a denser array of relays in the test head and uses the system bus for communication, eliminating I2C driver circuitry and freeing up valuable loadboard space.
Up to 16 PMUX02 cards can be installed in an EXA Scale system; the exact number depends heavily on the specific customer application and site count. An optional air cooling kit is also available. PMUX02 is fully compatible with its predecessor, PMUX01, enabling customers to utilize the same loadboards for their applications. In addition, PMUX02 is integrated into Advantest’s SmarTest 8 control software environment and takes advantage of the same powerful routing tools as PMUX01—which is crucial for agile application development.
Read MoreInterview with Keith Schaub on the Challenges of Testing Today’s Complex Chips
This Q&A is adapted from an article posted to the Semiecosystem blog by Mark LaPedus. It details a conversation with Keith Schaub, vice president of technology and strategy, regarding the test challenges for today’s complex AI chips, gate-all-around transistors, chiplets, and 3D NAND. The original article can be found here.
Q: How has semiconductor test changed over the years?
A: IC test has undergone significant changes over the years, evolving alongside the increasing complexity of semiconductor devices. Initially, testing focused on basic functionality, but as devices grew more intricate, the need for more advanced testing methods emerged. The ATE industry responded by developing new, more capable testers to handle higher pin counts, faster speeds, and greater integration. There was also a shift from purely functional testing to structural testing, which provides deeper insights into the integrity of the chip’s design and manufacturing process. In recent years, system-level testing (SLT) has become increasingly important, enabling verification of complete systems and ensuring interoperability of components. Modern IC tests now include sophisticated techniques such as built-in self-test (BIST) and scan testing, enabling more thorough verification. Additionally, the rise of system-on-chip (SoC) and other advanced technologies has driven the development of testers that can handle multiple functions simultaneously. This IC testing evolution reflects the semiconductor industry’s continual pursuit of higher quality, performance, reliability, and efficiency.
Q: What challenges do you encounter when testing AI devices?
A: Testing AI chips and accelerators presents several significant challenges due to their complexity and scale. These devices often feature large die sizes, billions of transistors, and dozens to hundreds of cores running at different speeds, depending on workloads. This variability increases the importance of advanced thermal management and control. Ensuring performance and reliability in such dense circuitry requires highly sophisticated ATE capable of handling high-speed interfaces and extreme thermal performance. Hotspots are a critical concern; not only understanding where they occur but being able to predict when they’ll occur during testing is vital for effective thermal control. Comprehensive validation is needed to ensure these chips perform optimally under diverse conditions, particularly in managing power densities and minimizing thermal hotspots. The integration of AI processors with other system components necessitates thorough SLT to verify overall system functionality and interoperability. Additionally, the rapid evolution of AI technology means testing methodologies must continually adapt to keep pace with new architectures and innovations. Overall, these challenges underscore the need for cutting-edge testing solutions to ensure the reliability and performance of AI semiconductor devices.
Q: Tell us more about system-level test. When do you use it in the test flow?
A: SLT is a comprehensive testing methodology used to validate the functionality, performance, and interoperability of semiconductor devices within their intended system environments. Unlike traditional testing methods that focus on individual components, SLT evaluates the entire system, ensuring that all integrated parts work seamlessly together under real-world conditions.
Over the years, SLT has evolved from being an optional insertion to a mandatory step in the test flow, particularly for complex devices such as AI chips, processors, and SoC solutions, where multiple functionalities and high integration levels are involved. SLT is typically used in the latter stages of the test flow after initial component-level tests have been performed. It follows traditional tests like wafer sort, package test, and burn-in, providing an additional layer of assurance by verifying the complete system’s behavior. For example, in the case of an AI processor, SLT would involve running actual AI workloads and applications to ensure the chip performs correctly within the end-user system. This helps identify any issues related to power management, thermal behavior, and interactions with other system components that might not be detected during earlier test stages.
Q: What new challenges does the transition to gate-all-around (GAA) transistors present?
A: The transition to gate-all-around (GAA) transistors at the 3nm and 2nm logic nodes presents several new challenges for testing. GAA transistors offer improved performance and power efficiency compared to finFETs, but their unique structure and increased density introduce complexities in test processes. One of the primary challenges is ensuring accurate characterization and validation of these advanced transistors, as their electrical properties can be more sensitive to variations in manufacturing processes. Moreover, the increased device density at these nodes requires more sophisticated ATE with higher resolution and precision. Thermal management becomes even more critical due to the higher power densities, necessitating advanced thermal testing techniques to identify and mitigate hotspots. The integration of GAA transistors also demands enhanced DFT and BIST strategies to ensure comprehensive coverage and efficient testing processes. The rapid evolution of these technologies requires continuous updates to test methodologies to keep pace with the latest advancements in GAA transistor design and fabrication. Overall, while GAA transistors at 2nm and beyond promise significant performance benefits, they also necessitate advanced and adaptive testing solutions to address the new challenges they bring.
Q: What are some of the test challenges and ATE solutions for chiplets?
A: Chiplets are generating significant attention in the semiconductor industry due to their potential to enhance performance and flexibility in chip design. However, they introduce several unique test challenges, such as ensuring seamless integration and communication between multiple chiplets within a single package, requiring rigorous testing of interconnects and interfaces. Ensuring known good die (KGD) is critical, as a single defective chiplet can render the entire package unusable, leading to high costs. To address this, shift-left strategies are increasingly important, involving early and comprehensive testing during the design and pre-assembly phases, leveraging AI techniques to enhance test coverage and predict potential failures. The heterogeneous nature of chiplets necessitates highly adaptable ATE capable of handling diverse test requirements. Additionally, SLT is crucial to verify the functionality and interoperability of the combined chiplets under real-world conditions. Thermal management and power delivery are critical, as multiple chiplets within a confined space can lead to hotspots and power distribution issues. Advanced thermal testing techniques and power analysis are required to identify and mitigate these problems.
ATE solutions are evolving to provide higher channel counts, greater flexibility, and improved precision. DFT features, such as BIST and boundary-scan, are increasingly integrated into chiplets to facilitate efficient testing. Overall, while chiplets offer exciting possibilities for innovation, their successful implementation hinges on advanced and flexible ATE solutions, ensuring KGD and employing shift-left strategies enhanced by AI.
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