Industrial Solutions for Machine-Learning-Enabled Yield Optimization and Test

This article summarizes the content of a paper developed and presented by Advantest at ETS 2022.

By Sonny Banwari, Vice President, Advantest Cloud Solutions, and Matthias Sauer, Applied Research Project Manager, Advantest Europe

According to market research firm Gartner, Inc., in assessing the completion rate of data science projects, as well as the bottom-line value they generate for their companies, only between 15 and 20 percent of these projects are ever completed. Moreover, of those that do manage to reach completion, less than 10 percent of them generate value, according to feedback provided by corporate CEOs. The bottom line: less than 2 percent of data science projects ever get completed AND deliver value. How can this squandering of corporate investment and effort be alleviated? One way is through the use of advanced machine learning (ML) techniques.

However, implementing ML in online manufacturing test poses its own set of challenges. ML-based applications challenge traditional test flows and infrastructures, as they require:

• Large amounts of data, often through multiple insertions spread geographically across multiple continents and located at various corporate entities depending on the position in the value chain;
• A secure, scalable and integrated compute infrastructure based on open standards; and
• A dynamic test execution infrastructure.

Some of these properties actually conflict with traditional test setups, which results in non-standard test flows and creates extra work that impacts time to market and return on investment – and, notably, slows success and adoption of ML applications.

Repeatability and reproducibility are essential to test procedures, particularly for automotive and other markets that rely on standardization and a high degree of compatibility. This requires establishing more structured thinking around ML and its impact on test. Figure 1 illustrates an industry-ready ML lifecycle designed to bring data science to the test floor.

 Figure 1. The four key steps of an ACS-powered machine-learning lifecycle are shown here.

ACS enables the ML ecosystem

Advantest Cloud Solutions (ACS) is a highly secure scalable data platform enabling an open solution ecosystem that helps customers address the most pressing challenges of the Smart Manufacturing era. The open aspect of the ecosystem is essential, as it allows any company along the supply chain not only to use it but to add value, create partnerships, deploy their own solutions, etc. ACS provides the vital infrastructure piece, as well as a wide range of development offerings through the ACS Solution Store, while Advantest provides other software products and services that customers can purchase when they need supplemental services to augment or enhance their existing deployments. Let’s take a brief look at each of the four key steps of the ML lifecycle.

Problem exploration and understanding

The earlier users seek to identify problems in the manufacturing process, the more data they require. Early bad-die detection is a vital component of this effort, as predicting likely failures post-packaging can help to significantly reduce costs and improve quality in the packaging process. To achieve this requires large amounts of high-quality data. Figure 2 shows the traditional test flow without benefit of ML techniques at left. At right, our ACS technology assesses data gathered from prior insertions and correlates it to accurately predict problems, enabling the user to circumvent them by fixing problems at the root cause, thus preventing bad die from reaching downstream test insertions. This reduces not just the cost of test but also the cost of the materials and processing needed as chips travel through the three-month long manufacturing process across continents and companies.

Figure 2. Using Advantest ACS techniques, customers can omit bad die early in the test cycle to reduce packaging costs and improve quality.

Model engineering

Model engineering is a crucial step for implementing assessed business requirements and turning them into a data-driven ML application, either using a custom implementation or employing pre-defined solution from the ACS Solution Store.

To evaluate the “ACS Yield Optimization” Reference App described above, we compiled a real-world dataset containing more than 200 relevant rest results per die from probe test and multiple fail bins from final test.

Running ACS-driven data analytics on the compiled, de-duped data, using one device under test (DUT) ID per entry, the tool uses deep learning-based variable selection to determine the variables of greatest influence on yield. It then creates new probe test limits based on the distribution of this data, removing false passes and confirming yield improvement. In the aforementioned case, the result was a 5% improvement in yield, from 88% to 93%, which translated to six-digit savings per year in U.S. dollars.

Figure 3. ACS Yield Optimization uses deep learning to analyze and optimize variable, resulting in higher yields and significant cost savings.

Deployment and execution

This refers specifically to secure, high-performance test floor integration of ACS with traceable deployments, as noted in Figure 1. Advantest purposely designed our ACS suite of tools not only for optimal results, but also for ease of use. Figure 4 shows our ACS Edge™ core product, which includes the ACS Edge Server and ACS Container Hub.

ACS Edge is a high-performance, highly secure edge compute and analytics solution that enables ultra-fast algorithmic AI decision-making with millisecond latencies during test execution. It connects to the user’s test equipment via a private, high-speed encrypted link and uses the advanced container hub to run the user’s protected applications while protecting and keeping secure the user’s data and analytics.

Figure 4. Advantest ACS Edge and available extensions help customers easily and securely integrate ACS into their test flow, enabling them to realize the full benefits of its ML-enabled capabilities.

Monitoring and validation

For models to move from the lab to volume production, they must be monitored for any unexpected behaviors resulting from changes in the product design or the test environment. The effectiveness of an optimization must be validated using real-world scenarios in order for a data science project to reach completion and contribute to a company’s overall value.

Semiconductor production is highly influenced by process variations from die to die, wafer to wafer, or lot to lot, particularly at smaller process nodes with tighter geometries that afford less room for deviation. Thus, there is an inherent risk of “silent” model degradation of when a learned process characteristic changes, potentially impacting the quality of the model (yield, test time, device quality, test escapes, etc.) ACS employs a continuous learning loop with continuous monitoring, greatly reducing this risk so that models retain their integrity.

ACS Solution Store 

Another key piece of the ACS ecosystem that helps create a unified, repeatable workflow is our ACS Solution Store, which provides ease of access to ACS real-time data infrastructure solutions and software applications. This online platform enables customers to discover, purchase and securely deploy all available ACS solutions from Advantest and a broad spectrum of analytics ecosystem partners across the semiconductor lifecycle process. In addition, the ACS Solution Store enables application developers from these partner firms to publish, promote, distribute and manage their Advantest-certified apps.

This latest aspect of the ACS offerings is vital to maintain an open ecosystem, as it facilitates access to all ACS offerings for customers, as well as giving them and our partners the ability to develop and publish their own apps. This allows sharing of new capabilities and best practices so that the capabilities of our ACS technologies can be optimally leveraged across companies throughout the semiconductor ecosystem.

We continue to expand and evolve our Advantest Cloud Solutions to meet evolving customer demands. By putting ACS in place within their test environments, customers can ensure they’re armed and ready for the future of semiconductor test.

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Engineering Test Station Facilitates Post-Silicon Validation

By Adir Zonta, Advantest

The semiconductor market is evolving, with devices becoming more complex as chip designers add cores and pursue 2.5D and 3D integration strategies. This complexity presents challenges extending from design and simulation through system-level test (SLT), where a device is exercised in mission mode, booting up an operating system and running end-user code, for example.

These challenges arise from the exploding volumes of test data that must be acquired and analyzed throughout the design and test process. In addition, chipmakers are increasing the number of new product introductions (NPIs) per year as they diversify their product portfolios.

The exploding data volumes and proliferating NPIs in turn are combining to increase the need for flexible test processes and equipment, and they are straining engineering teams and their facilities. 

Worst case, a company could be faced with building a new engineering facility, either next door to an existing one or in a remote location. 

Ideally, a company would find a way to increase its capacity without expanding its engineering facilities. The arrival of first silicon presents a particular pressure point, when companies must deploy teams of engineers to perform device bring-up, pattern generation, and characterization.  

Engineering test station

Advantest is addressing the needs of such customers by augmenting its V93000 EXA Scale SoC Test System lineup, which targets advanced digital ICs up to the exascale performance class while lowering cost of test and shortening time to market.

Advantest’s latest offering in the family is the V93000 EXA Scale EX Test Station—a state-of-the-art engineering platform for complex device bring-up that supports structural and functional test.

To enable a fourfold increase in tester capacity within the same engineering lab footprint, the EX Test Station fits under Advantest’s single-site M4171 automated handler, which brings automated device loading, unloading, and binning into the laboratory environment.

The handler features integrated active thermal control (ATC) over a -45 to +125°C range. ATC supports fast data collection and can improve temperature cycle testing throughput by 40% compared to manual thermal-control approaches. The handler also can include a camera to facilitate remote work and 24/7 availability. The total test-cell footprint measures 0.56 m by 0.82 m, allowing six test cells to fit comfortably within a 5-m by 5.5-m laboratory space (Figure 1).

Figure 1. Typical engineering layout of EX Test Stations with M4127 handlers.

To further save space, three, six, or nine EX units can share a single cooling unit. Furthermore, the tester, handler, and thermal-control unit form a highly automated combination to conveniently and quickly gather the high-volume data needed for today’s successful silicon bring-up activities without continual intervention by engineers. Recent experience with remote work has demonstrated its feasibility for test-engineering applications. Rather than having a complete team of engineers on site, a single operator can be available to provide hands-on assistance to address any issues observed by the engineers working remotely.

The EX Test Station employs Advantest’s Xtreme Link technology, designed specifically to provide high-speed optical data connections, embedded computing power, and card-to-card communications for ATE.

Although not intended for use in high-volume manufacturing (HVM), the EX Test Station does have full throughput capability and is therefore suitable for testing initial engineering batches efficiently. In addition, it helps to ensure seamless flow between the engineering and HVM environments. To ensure a smooth transition to Advantest’s V93000 production-test system with perfect correlation, the EX Test Station includes a V93000-compatible DUT board and uses V93000 SmarTest 8 software as well as V93000 instruments (Figure 2).

Figure 2. The EX Test Station with V93000 DUT interface and three universal slots.

Specifically, the EX Test Station accommodates up to three EXA Scale cards, including Advantest’s XPS256 Extended Power Supply (XPS) device power supply (DPS) card, which delivers 256 channels of power at current ratings in the thousands of amperes at voltages below 1 V.

In addition, the EX Test Station accepts the Pin Scale 5000 digital card, which achieves 5-Gb/s speeds and is designed to address the explosion of scan data volumes inherent in large digital designs.

The EX Test Station also works with members of Advantest’s Link Scale™ digital-channel-card family for the V93000, which enable software-based functional testing of advanced semiconductors. Link Scale cards also support USB/PCI Express (PCIe) scan testing and address testing challenges that these high-speed interfaces present. During test, the Link Scale cards communicate with the DUT through the USB or PCIe interfaces running in full protocol mode. This approach tests a device in its normal mode of operation using firmware and drivers similar to those in the target application—thereby adding System-Like-Test™ capabilities to V93000 EXA Scale systems, including the EX test station. System-Like-Test enables tests that might otherwise be applied at SLT to shift left to an ATE system.

The Link Scale cards also enable the reuse of pre-silicon functional tests by leveraging the Portable Test and Stimulus Standard (PSS), which is supported by major electronic design automation (EDA) tools and which significantly improves test quality and reduces time to market.

Finally, the EX Test Station accommodates a utility card and includes a module with 64 utility lines and a 5-V utility supply. (An external utility power supply is optional.)

The cost-optimized EX Test Station with engineering cart, integrated power supply, peripherals, and shared cooler helps control facility costs through its 4x improvement in engineering floor capacity and by reducing power requirements—it operates on single-phase, 200- to 230-V, 30-A power.

Conclusion

The drastic increase in test-data volume coupled with a proliferation of NPIs is spurring on an increasing demand for investment in engineering. Advantest’s EXA Scale EX Test Station represents a cost-effective optimized solution that performs structural and functional test to support the bring up, debugging, and characterization of complex digital devices. Combined with the M4171 handler, it forms a highly automated engineering test cell with remote-access capabilities. The complete test cell offers a fourfold increase in engineering-lab capacity without any increase in footprint while minimizing engineering costs and cutting time to market.

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Data Collection and Analysis Drives Semiconductor Test in the Era of Chip Convergence

This article is a condensed version of an article published February 16, 2022, on JIWEI Net. Adapted with permission. Read the original article at https://www.laoyaoba.com/html/share/news?source=app_android_v2&news_id=806699&sign=5ab5d193a7e37db4e4b7728f73e6a208

In the Age of Convergence, many forces are driving continuous advancement of semiconductor testing technology. As more and more functions are carried on a chip, and technology grows more and more complex, the number and types of test steps must be multiplied – leading, in turn, to increased test costs. Semiconductor test equipment requires ultra-long “standby,” which is an asset-heavy investment in semiconductor manufacturing plants, with a life cycle of at least 5 to 10 years. In an intelligent world where chip technology and processes are rapidly upgraded and iterated, such equipment must be able to meet increasingly complex testing needs at any time.

As a result, test and measurement solutions must expand to address the entire semiconductor industry value chain. This includes not only the traditional “center” of testing (IC production processes, wafer test and final test), but also greater integration with IC design and more system-level testing (SLT) at the product level, plus connectivity, including the cloud, artificial intelligence (AI) and Big Data.

Advantest and PDF Solutions’ collaboration [first announced in July 2020], targets these expanded capabilities. By combining PDF Solutions’ Exensio platform and its Data Exchange Network (DEX) with Advantest’s advanced test equipment (ATE), customers can connect and analyze data anywhere in the semiconductor supply chain, helping them improve product yield and reduce test costs.

The two companies’ jointly developed product – ACS Dynamic Parametric Test (DPT) – integrates PDF Solutions’ Exensio data analysis products with Advantest’s V93000 parametric test system, enabling real-time optimization of parametric tests on the V93000 test platform and reducing manual interaction. The figure below illustrates the ACS DPT solution elements and functionality.

The balance of the article comprises an interview (also excerpted) with executives from both companies: Advantest’s Keith Schaub, vice president of strategy and technology, and Sonny Banwari, ACS vice president of business development; and PDF Solutions’ Guanyuan (Michael Yu), vice president of sales and operations, and David Park, vice president of marketing.

What are the key benefits of the Advantest-PDF collaboration, and why are they important for the semiconductor industry?

Keith:  Advantest has a long history in semiconductor testing, and we are the market leader in high volume manufacturing of semiconductor test products, with a range that spans from post-silicon validation, all the way to system-level test. Now, there is a lot of big data coming out of the test eco-system, and the industry has realized the future is using tools like AI and machine learning to mine data value, to improve the operational efficiency of the entire ecosystem, and of the entire supply chain.PDF Solutions is well established and strong in data analytics, and an ideal partner for bringing this advanced technology to the fore.

Michael: Advantest is the world’s leading supplier of semiconductor test equipment. Over the decades, it has amassed an enormous amount of knowledge and data related to semiconductor testing. PDF has always focused on data analysis of the entire semiconductor industry chain. The key point of this cooperation is to interconnect test-related data with the entire industry chain. For example, some data before testing, such as manufacturing-related data, can help to decide which devices to test and how to improve testing efficiency and quality. At the same time, data from these test cells can be brought forward to the subsequent steps of the supply chain and can also be fed back to obtain a more reliable and efficient test plan.

While the semiconductor industry is data-intensive, it is relatively backward in data analysis. What are the major obstacles? How will your joint data analytics-based products impact the industry?

Keith: The global semiconductor industry is in a period of rapid growth, and the huge market size brings huge growth opportunity for companies throughout the entire industry supply chain. At the same time, end-user applications are increasingly diverse and complex, with higher requirements for the quality and reliability of electronic components such as IC chips. Making test scheme coverage more comprehensive increases test cost. How do we control the cost of testing under the premise of ensuring higher quality? By mining the value of semiconductor data.

ACS powered by PDF Exensio is equivalent to providing the industry with an infrastructure platform for data analysis of the entire semiconductor supply chain. PDF Exensio can help collect data from semiconductor chip fabrication, test, and system-level test. With advanced algorithms, integrated workflows, and solutions delivered by ACS, more valuable information can be gained from the data generated by supply chain equipment and testing, resulting in shorter production times and higher overall equipment efficiency.

Sonny: As an example, the global chip shortage is a crisis for all industries, especially the automotive industry. In fact, this crisis has further forced carmakers to optimize products and technologies to deal with the chip shortage. The cooperation between Advantest and PDF Solutions is doing a similar thing: improving product yield through data analysis and providing customers with better products. It’s just reducing a company’s costs and improving its profitability, but it’s giving an opportunity for the entire semiconductor ecosystem to upgrade.

Michael: Indeed, to ensure the quality and reliability of chips, especially automotive chips, you need extensive testing, and that takes tremendous time and effort. But if we can adopt a traceable system and integrate the data of the entire production process, we can use AI and machine learning to tell us what to test, and what’s the most efficient way to perform the test. Instead of just one size fits all, with data analysis obtained through AI and machine learning, we can carry out personalized test plans for different quality requirements and find the best test results in the shortest time.

David: About five years ago, people were hesitant about going to cloud, mainly due to concerns about data security and privacy, especially in the semiconductor industry. This is the biggest obstacle for data analysis in the semiconductor industry. How to get enterprises across the supply chain willing to share data is a key step, and this is one aspect of what we are trying to do, to create a safe data sharing ecosystem. For example, both Advantest and PDF are involved in an initiative out of the GSA (Global Semiconductor Alliance) called TIES (Trusted IOT Ecosystem for Security), with the goal to bring together all the different players in the semiconductor supply chain, from design to manufacturing, packaging, and testing, to jointly form a secure trusted data sharing ecosystem.

Working remotely has also greatly promoted investments in cloud infrastructure, and the semiconductor industry is now a bit more open to moving data to the cloud. Being in the cloud will bring a more efficient and convenient data ecosystem to the entire semiconductor supply chain, for both scalability and computing performance.

In terms of empowering the semiconductor industry with intelligent means, such as big data analysis, cloud, and AI, what are the new trends in the future?

Keith: For a long time, the industry tended to use a one-size-fits-all general test solution, but different applications require customized test scenarios. However, with the increasing complexity of semiconductor process technology and the diversity of application requirements, the quality requirements for chips and other electronic components will also be different. Moreover, in the current environment of supply chain shortages, optimizing the test plan with different quality requirements for devices and use the big data analytics to control the test cost is vital. This is also what we are doing in cooperation with PDF Solutions.

Sonny: In the future, we will also increasingly tap the potential of AI-based and machine learning to develop more killer applications. Advantest and PDF understand each other, and we look forward to working together to elevate the power of machine learning to a new level in semiconductor testing and data analysis.

Michael:  As technology progresses, the manufacturing process becomes more and more complex; in addition, as chip size increases, there are more and more functions, which means that the amount of testing will also increase, and the whole process will generate an increased amount of data. And how to effectively leverage all of this data – through machine learning, AI, cloud computing and other methods, including data mining, to improve the overall efficiency of semiconductor manufacturing and optimize costs – will become more and more important.

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Harnessing the Power of Data in Semiconductor Test

This article is a condensed version of an article published in the Winter 2021 issue of MEPTEC Report. Adapted with permission. Read the original article at https://issuu.com/mepcom/docs/meptec_report_winter_2021?fr=sNTRhZDE1OTk3NzE

By Ken Butler, Strategic Business Creation Manager, Advantest America

Every day, new methods are being developed to harvest, cleanse, integrate, and analyze data sources and extract from them useful, actionable intelligence to aid decision-making and other processes. This is true for a variety of industries, including semiconductor design, manufacturing, and test.

Moore’s Law (Figure 1) may be slowing with respect to traditional scaling of transistor critical dimensions. But as engineers continually develop ingenious ways to pack more functionality into a single product, e.g., 3D fabrication, multi-chip packaging, stacked die, and buried power rails (to name a few), the density of components in products is also increasing rapidly. Further driving this growth is an unprecedented increase in semiconductor demand, fueled by heightened online retailing, work-from-home scenarios, and transportation electrification.  

Figure 1. Illustration of Moore’s Law from 1970 to 2020.

One metric for tracking the overall semiconductor output is the number of transistors fabricated per year. VLSI Research [now part of TechInsights] has estimated that quantity for each decade since the inception of Moore’s Law, as shown in Figure 2, and estimates total output for 2021 was approximately 1.6×1021 (1.6 billion trillion) transistors!

Figure 2. Estimated number of transistors sold annually.

By even a highly conservative estimate, the test data resulting from this hard-to-imagine number of devices would be greater than 40 terabits per second! All that data must be analyzed – not only to determine which components are good and bad, but also for many other “bits” of intelligence: passing but “suspect” components, whether or not the product containing the components meets its datasheet and reliability requirements, whether or not the manufacturing and testing processes and equipment remain healthy and under control, and a host of other critical information.

Moreover, this estimate only addresses data generated by the test function and doesn’t include design, fab and test equipment, sensor, inspection, and calibration and maintenance data. So, we must deal with an ocean of data to streamline and optimize our production processes. It is a prime example of what Jack Morton from Bell Labs called the tyranny of numbers way back in 1958 [1].

Table 1 lists additional industry trends and associated test challenges that are changing today’s semiconductor test solution landscape.

Table 1. Industry trends and semiconductor test challenges.

Two facets of test significantly influenced by these trends are product quality and test cost.  New and subtle defect mechanisms, combined with the push toward ever higher levels of quality, increase the amount and complexity of testing and screening that must be performed to ensure low parts per billion test escape rates. All this testing, in turn, consumes more test time, thus increasing the cost of test. Semiconductor suppliers are looking largely to data analytics to solve these problems and keep the cost of test at reasonable levels without any compromise in outgoing quality or reliability. Let’s look at some examples of solutions Advantest is pursuing.

Dynamic parametric test

One of the earliest test steps performed on semiconductor devices is parametric test, also known as e-test or wafer acceptance test (WAT), which is performed during and following wafer manufacturing. The structures being tested can be individual transistors, resistors, and other components that are fabricated in the scribe lines, which are the small spaces between each die on a wafer, as illustrated in Figure 3 [2].  While these structures fill most of the scribe lines on the wafer, testing is typically limited to a few sites spread across the wafer surface.

Figure 3. Parametric testing involves structures fabricated in the wafer scribe lines between the die.

The test measurements provide valuable data used to monitor the health of the manufacturing process.  When anomalies are detected, typically the material flow is stopped so fab engineers can determine the cause of the problem. That often involves retesting material, collecting additional information, and performing additional manual analyses – all of which is disruptive and potentially costly to fab operations.

Dynamic parametric test (DPT) was created to automate and speed resolution of these types of excursions. Using DPT on an Advantest V93000/SMU8 parametric tester with PDF Solutions Exensio® software, a set of user-definable rules is established and checked during parametric testing. When the rules detect an issue, actions are immediately triggered to accelerate root-cause identification.

This process is illustrated in Figures 4 and 5. In this example, a diode measurement is being performed.  An out-of-specification measurement is detected, which triggers a DPT rule, and the test flow quickly adapts to a sweep of additional diode measurements across additional e-test sites on the wafer.  This real-time update collects the additional data necessary to diagnose the cause of the issue without requiring a stoppage of material flow and the reloading and retesting of aberrant wafers, thus saving both time and cost.  In the example cited here, the resulting root cause was quickly narrowed to a reticle or etch issue.

Figure 4. DPT detects out-of-spec diode parametric test.

Figure 5. DPT adaptively adjusts parametric test execution to collect additional data.

Production test edge computing

Downstream from parametric test is production testing. Wafer probe or wafer sort testing is performed while devices are still on the wafer. After good die have been singulated and packaged, they are subjected to final or package test. Other optional steps include system-level test, where die are subjected to a longer test that more closely resembles actual in-system operation, and burn-in, where the devices are tested, up to several hours, at elevated voltage and/or temperature to accelerate early life failures and measure product reliability.

Historically, production tests are a “one size fits all” proposition – for a given product, the same suite of tests is applied to every die. What’s desired, however, is to use data emerging from the test process itself to modify test content and execution so that each die sees the “right” tests. This process, which enables optimized deployment of test resources, is called adaptive test.

One form of adaptive test is executed as a post-test operation, e.g., wafer sort data is analyzed after the fact, and downstream final test operations are adjusted based on that analysis. However, semiconductor suppliers are also pursuing real-time adaptive test processes during production, in which test flow and content are altered during test execution, with low millisecond latencies. Several examples published in recent years describe scenarios that would work well when deployed as real-time adaptive test applications, including adaptive limit setting during search routines, predictive device trim, classifiers and device clustering, and burn-in optimization via at-risk device identification. [3] – [12]

Advantest developed ACS Edge to address this need for very fast, low-latency and highly secure analytics during production test. A high-performance compute platform with a dedicated, secure communication channel to the tester, ACS Edge wraps analytics in Docker containers to ensure reliable execution regardless of the compute environment’s configuration. All information related to the analytics and the data being analyzed is encrypted to prohibit unauthorized access that could compromise sensitive proprietary information.

Conclusion

As semiconductor product data sources become larger and more diverse, IC developers and manufacturers are challenged more than ever to deliver devices on time with highest quality and at the lowest possible cost. They are looking to advanced data analytics to extract intelligence needed to adjust manufacturing and test flows to adapt to an ever-changing environment. Test plays a pivotal role because it directly interfaces with each device to extract and analyze the data needed to monitor and control product quality and performance. DPT and test edge computing are just two approaches being deployed into production to address these challenges – we can expect to see more new solutions as innovation in manufacturing and test data analytics continues.

 

References

[1]	Various, “Tyranny of numbers,” 2021. [Online]. Available: https://en.wikipedia.org/wiki/Tyranny_of_numbers. [Accessed 22 Oct. 2021].
[2]	M. Bhushan and M. Ketchen, “Electrical Tests and Characterization in Manufacturing,” in CMOS Test and Evaluation, New York, NY, Springer, 2015.
[3]	D. Neethirajan, X. C. K. Subramani, K. Schaub, I. Leventhal and Y. Makris, “Machine learning-based noise classification and decomposition in RF transceivers,” in IEEE VLSI Test Symposium, Monterey, CA, 2019.
[4]	C. Xanthopoulos, D. Neethirajan, S. Boddikurapati, A. Nahar and Y. Makris, “Wafer-level adaptive Vmin calibration seed forecasting,” in Design, Automation and Test in Europe, Grenoble, France, 2019.
[5]	M. Eiki, K. Schaub, I. Leventhal and B. Buras, “In test flow neural network inference on the V93000 SmarTest test cell controller,” in IEEE International Test Conference, Washington, DC, 2019.
[6]	V. Niranjan, D. Neethirajan, C. Xanthopoulos, E. De La Rosa, C. Alleyne, S. Mier and Y. Makris, “Trim time reduction in analog/RF ICs based on inter-trim correlation,” in IEEE VLSI Test Symposium, Virtual, 2021.
[7]	T. Y.-T. Kuo, W.-C. Lin, E. J.-W. Fang and S. S.-Y. Hsueh, “Minimum operating voltage preiction in production test using accumulative learning,” in IEEE International Test Conference, Virtual, 2021.
[8]	M. Shintani, M. Inoue, T. Nakamura, M. Kajiyama and M. Eiki, “Wafer-level variation modeling for multi-site RF IC testing via hierarchical Gaussian process,” in IEEE International Test Conference, Virtual, 2021.
[9]	M. Liu and K. Chakrabarty, “Adaptive methods for machine learning-based testing of integrated circuits and boards,” in IEEE International Test Conference, Virtual, 2021.
[10]	S. Traynor, C. He, K. Klein and Y. Yu, “Adaptive high voltage stress methodology to enable automotive quality on finFET technologies,” in IEEE International Test Conference, Virtual, 2021.
[11]	C. Nigh, G. Bhargava and R. Blanton, “AAA – Automated, on-ATE AI debug of scan chain failures,” in IEEE International Test Conference, Virtual, 2021.
[12]	C. He, P. Grosch, O. Anilturk, J. Witowski, C. Ford, R. Kalyan, J. Robinson, D. Price, J. Rathert and B. Saville, “Defect-directed stress testing using I-PAT inline defect inspection results,” in IEEE International Test Conference, Virtual, 2021.

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Trends in Testing: New Challenges Create New Opportunities

By Doug Lefever, Senior Executive Officer, Advantest Corporation, and President and CEO, Advantest America

As advancements in semiconductors and microelectronics soldier ahead into emerging, even uncharted, territory, new test challenges arise. To that end, let’s look at a few key trends and challenges that are driving opportunities for innovation in the test sector.

Technology convergence has been a buzzword for some time, and this trend is only going to intensify with the heightened need to move, access, and analyze massive volumes of data. As a result, data analytics technologies (Big Data, artificial intelligence [AI], and machine learning) will continue to play a vital role in driving test efficiencies – not just operational, e.g., improving overall equipment efficiency (OEE), but also transformational: enabling data to feed forward and backward between test insertions, as well as outside of test. The reality is that the lines are blurring between the front and back ends of test, and the insertion points change, depending on device type and lifecycle status. So, the test flows that happen throughout the lifecycle of the device need to be flexible.

Complex high-performance computing (HPC) and AI devices are growing very large, and because of interposers and bridging, their power requirements can exceed 1000W. This means that we need to be able to manage temperature with a high degree of precision during testing. These large devices also require additional compute and analytics capability during test. To this end, we developed our ACS Edge solution, which essentially adds a supercomputer alongside the tester to open up compute power and start to enable real-time adaptive test.

With these developments, the system will become enormously complex, requiring verification of entire systems (hardware, firmware/embedded applications, and software). This means we’ll be seeing a broader deployment of system-level testing (SLT) for both systems and modules, as well as SLT/ATE at the probe level for known good die, including active thermal management solutions. To this end, we’ve incorporated into our offerings the test-related accessories we acquired upon purchasing Essai, including sockets, thermal control units and other test subassemblies. Our value proposition rests in our ability to address the full hardware stack and in the comprehensive nature of our offerings.  

In the broader test arena, generation, validation, and optimization of required test content such as scan vectors, built-in self-test (BIST), and functional test (software code) will need massive support and cooperation between the EDA and ATE industries. Advantest has established strong relationships with the leading EDA providers to help drive these efforts. The industry is also going back and mixing functional tests more with structural tests, and more design-for-test (DFT) techniques are being added. While increased scan, serial high-speed scan over USB, and PCIe ports are being used, that still isn’t enough, which brings us back to SLT continuing to be deployed.

For 5G, test solutions are largely in place. Some high-volume manufacturing (HVM) device interfacing/interconnect technologies like over-the-air (OTA) are coming along, while test development is starting for advanced millimeter-wave (i.e., THz, 6G). There will also more use of on-chip sensors and agents to monitor device performance all the way through the fab, assembly and in-field. This traceability is vital to ensuring ATE plays a critical role in pulling data from sensors – this heightened need for data extraction and analysis is a recurring theme that permeates everything going forward.

Continued electrification of cars will also drive lots of growth in test, including challenging areas like high voltages – i.e., those greater than 1kV – which require different kinds of methodologies. These higher voltage requirements are also needed for silicon carbide (SiC) applications in vehicles. SiC, like gallium nitride (GaN), has been around for a long time and is finding new life in applications such as battery management. We can cover this with our mixed-signal configurations and our integrated power solutions.

With respect to packaging, we expect to see a bifurcation in the industry: HPC/AI will move to 2.5/3D ICs, while mobile will remain on monolithic 2D for a little while longer. We’re already into 2.5 and 3D, and we have been for some time. However, with hybrid bonding and die stacking, we’re moving into 3D IC. When that is fully implemented, it will bring some tough new challenges. We believe a holistic approach is required to create high-power solutions that will then be coupled with other chips in a package.

In addition, there will be new approaches to address the “memory wall,” such as large eRAMs, 3D stacked RAMs, co-packaging on 2.5D or access via serial I/O. Power consumption of I/Os may also drive the integration of optical I/O. The first step will be co-packaged optics (CPO), which involves heterogeneous integration of optics and silicon on a single packaged substrate aimed at addressing next-generation bandwidth and power challenges. 

As you can see, many technology trends have test requirements that overlap or coincide, with demands created by massive amounts of data generation and processing playing a massive role. Testing at the exascale level requires powerful equipment that can handle the challenge. We are meeting this challenge with our EXA Scale test system, built on our flagship V93000 architecture, which addresses the challenges of very high scan-data volumes, extreme power requirements, fast yield-learning and high-multisite configurations.

 

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Automotive Keyless Entry SoC Test Methodologies and Techniques

By Philip Brock, Applications Engineer & Consulting Manager, Louis Benton, Jr., Applications Engineer & Consulting Director, Advantest, and Jonvyn Wongso, Technical Staff Test Engineer, Microchip

Note: This article excerpts content from the Virtual VOICE 2021 Best Paper, voted on by conference attendees. Jonvyn Wongso, Daniel Marstein & Krishna Vangapalli from Microchip Technology co-authored the original paper, and their research and development efforts were invaluable to this project.

Passive Entry Passive Start (PEPS) technology has become standard in the automotive market for keyless operation. A secure wireless communication system, PEPS enables to lock and unlock the vehicle, start and stop the vehicle without physically using the key. Electronic functionality embedded in the key fob to interact with the vehicle (see Figure 1) includes passive start and stop, passive lock, remote keyless entry, immobilizer, key fob wake-up, and key fob localization. These functionalities are controlled by the primary modules embedded within the fob itself. The immobilizer provides access to start the vehicle when the key fob’s battery level is low by placing the fob at the start button and pressing it.

Figure 1: This diagram illustrates how components within the key fob correspond to functionality in the car itself.

The PEPS-to-vehicle ecosystem requires several key modules to function that includes a low-frequency (LF) transmitter, an immobilizer, a Radio Frequency (RF) transmitter (key fob) and transceiver (vehicle side), as well as a microcontroller (MCU). Each module in the key fob poses specific testing challenges and restrictions, necessitating a test plan and flow optimized for the testing of the key fob’s circuit, as shown in Figure 2. 

Figure 2: The key fob architecture depicts the main components within the key fob and a representation of how each component is tested on the Advantest V93000 test system.

The coverage percentages at the upper right in Figure 2 represent the overall test flow’s test time. Approximately two-thirds of the test coverage is dedicated to the LF structure (analog) and the MCU (digital), with another 19 percent focused on power management and parametric tests. The remaining 6 percent of the test coverage involves testing of the RF module with transmission functionality at sub 1 GHz band with no RF reception capability.

The combination of test requirements to accommodate all the different technologies housed within the PEPS key fob makes it an ideal device for demonstrating the versatility of the Advantest V93000 SoC test platform, including the AVI64 and PS1600 pin cards. A test solution is designed with comprehensive methodologies to test every module in the key fob. The balance of this article summarizes the key aspects of the test approach.

PEPS test methodology elements

Digital

Digital testing utilizes two standard methods to communicate to the IC:

• Serial programming interface (SPI) – Standard communication protocol is used to test all non-MCU (non-digital) structures via direct access to the RAM. However, due to the slow communication speed compared to HVSP protocol, the programming time to the EEPROM is approximately 10ms per byte.
• High-voltage serial programming (HVSP) – Used for FLASH and MCU core test with fast access to the EEPROM, this proprietary protocol is much faster than SPI, with a FLASH and EEPROM programming time of 3 to 4ms per page (each page is 16 bytes long).

One key digital test that has to be performed is to measure the time to program a page to the FLASH (16 bytes). The page program completion time varies between devices. The typical test method to measure and detect the end of the programming time is by implementing a match loop counter opcode in the pattern vector as the device asserts a state of a pin to high when the programming event has completed. However, the implementation of this method prohibits the use of the PS1600’s Time Measurement Unit (TMU) function on the same channel pin in parallel to measure the page program time accurately.

The test methodology developed involved the use of the Rapid Development Interface (RDI) API, a code structure that wraps Advantest’s standard application programming interfaces (APIs). The API is based on object-oriented programming that encapsulates firmware commands, enabling seamless execution of multiple commands. This creates a competitive advantage by dramatically streamlining the software development, and with the V93000’s multiport capability, it enables higher timing resolution that can be achieved on a specific pin or pin group. The use of the comparator functionality allows to strobe for a level change in the signal for a fixed amount of time.

Power Management

The Brownout detection circuit in the PEPS is a challenge to test to achieve optimized test time. In a typical test method, a voltage sweep is conducted from high to low to detect the brownout state threshold, followed by a voltage sweep from low to high to search for the recovery threshold level. An experiment was conducted with the implementation of four different test methodologies to determine the most optimized method to test the Brownout Detection circuit, summarized in Figure 3. In summary, the implementation of the Per Pin Parametric Measurement Unit (PPMU) as the Arbitrary Waveform Generator (AWG) yielded the fastest test time with minimal test instrument latency dependencies.

Figure 3: Investigation of four different brownout detection methodologies – PPMU as AWG methodology consumes a fraction of the test time in comparison with the other three options

Low Frequency Test

The Receiver Signal Strength Indicator (RSSI) circuit in the key fob indicates the proximity and location of the key fob with respect to the vehicle. The 3D LF pins are transponders with signal transmission and detection  at a frequency of 125 kHz with detection amplitude levels as low as 1.0 mV peak differential. The LF test requires a complex on-board circuitry in order to source AWG amplitude levels from 1 mV up to 8 V peak. Due to the real estate demand from the load board to implement these circuits with amplitude ranges, the extra-large size load board is used, extending out on both sides of the tester’s field. The RSSI value may only be read out after the completion of conversion of the LF signal level from a specific register in the device. In addition, there is a register that may be continuously read to check for status of the RSSI conversion.

Therefore, the proper test methodology for this test is to implement the Condition Go-No-Go (COGO) API from RDI to continuously check for the status of the conversion. This method corresponds to the device’s application. However, due to the inherent long latency to judge each event using COGO (described in Figure 3), a one-time fixed time delay was implemented prior to the readout of the RSSI conversion.

The other primary LF test involved the transponder, which is used for the immobilizer. The key fob that is placed at the start button of the vehicle will be energized by the vehicle’s coil that is located around the start button to enable communication between the key fob and the vehicle. This test requires both the AWG and Digitizer (DGT) instruments to source and capture the modulated waveform on the LF pins.

The communication between the key fob and the vehicle compromises of three stages as shown in Figure 4 – startup (energizes key fob), write mode (vehicle transmit authenticated message to key fob) and read mode (key fob responses with another authenticated message). The post processing of both the sourced and received waveform uses custom Digital Signal Processing (DSP) functions along with built-in V93000’s DSP APIs. 

Figure 4: Transponder communication between key fob and vehicle on LF pins on key fob.

RF Test

The Amplitude Shift Keying (ASK) modulation is used to transmit RF authenticated signal from the key fob to the vehicle. It is critical to test the duty cycle of the modulated signal that has a period of 12.5 us, toggled by an external pin when set in test mode. The device itself operates at a 2 us period. Therefore, multiport has to be implemented for the sequencer to drive two groups of ports at different periods. This test methodology also includes RF site interlacing technique, taking advantage of the V93000’s eight-site parallel test capability with 2 RF FE24 cards. Figure 5 illustrates the test criteria and methodology employed. Post-processing involves the capture of complex waveform, conversion of the waveform to rms in order to create the burst envelopes, performing moving average to filter out noise and searching for all falling and rising edges to calculate the duty cycle. 

Figure 5: The transmit ASK duty cycle test methodology is summarized here.

Software/hardware techniques

The LF testing requires sharing of the AWG and Digitizer instruments (MCE 4 source and 4 measure units) across 8 sites, thus increasing test time and reduces multisite efficiency. The implementation of SEMI_PARALLEL block in the test method enables execution of a single test cycle, hence maximizing multisite efficiency. Sequencers connected to AWG and DGT are placed in the SEMI_PARALLEL block as shown in Figure 6. Method 1 is the most common implementation. However, the setup pattern will be executed more than once on the same site. In contrary, method 2 is the least efficient but may be an option if the setup pattern may only be executed once to each site to avoid change of the state of the device.     

Figure 6: Shown here are the two most common SEMI_PARALLEL block test flow methods for shared resources.

Another test method technique implemented as part of the test solution includes the use of both RDI and MAPI APIs to resolve per site device failure on a specific mode or event as shown in Figure 8. RDI is used for the initial generation and execution of the pattern. MAPI APIs are subsequently used to re-execute the RDI generated pattern to specific failed sites. This method allows the recovery of the device(s) within the test method to save test time and not applying stimulus and retesting already passed sites.

Figure 7: The combination of RDI and MAPI usage enables device per site failures to be resolved.

On the hardware side, the use of relay driver circuit (SN74LS04DR followed by MDC3105LT1G) enables the drive of eight relays simultaneously such as G3VM-41QR10TR05 only by using a single utility pin. This technique enables the implementation of many circuit paths on the load board but omits the need of a PMUX card in the tester. Subsequently, the test load board design requires calibration of every signal path and circuit for each test site. There is an on-board EEPROM that stores the calibration offset and losses. Due to the limitation of memory space in the EEPROM, every calibration value is compressed using IEEE754 floating point standard. Depending on the accuracy requirement, this method enables greater than 50-percent compression rating of a decimal value. 

In summary, there are many challenges in both hardware and software development to create a test solution for optimized test time and efficiency, as summarized in Figure 8.

Figure 8: Summary and challenges of PEPS key fob test solution.

Since this device is targeted for automotive application, it has to be tested at cold, room and hot temperature ranges. Temperature variations affects the performance of the circuitry on the load board and has to be calibrated for each temperature range. The MCU core has to be tested at multiple different voltage level that requires synchronization of the pattern sequencer for each level change. In addition, testing the LF circuit requires extensive changes in the AWG’s amplitude level that requires additional setup and execution time that may increase test time and lower efficiency.

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