W2BI in the Spotlight at Mobile World Congress with New Test Automation Products for the Wireless Market

Advantest, together with W2BI ‒ an Advantest Group company that provides test automation products to help customers quickly launch high-quality smart devices ‒ showcased their newest test platforms for the wireless electronics market at the 2017 Mobile World Congress (MWC) in Barcelona, Spain.

The world’s most expansive exhibition for wireless technology and mobile devices, MWC serves as an annual springboard for many of the next year’s biggest announcements and rollouts of smartphones, tablets and other connected devices. To give you an idea of scale, MWC this year drew more than 108,000 attendees from 208 different countries and boasted approximately 2,300 exhibiting companies.

Within its booth, Advantest featured a suite of products for the mobile communications and Internet of Things (IoT) markets. This included the EVA100 tester, designed for highly efficient evaluation and measurement of analog/mixed-signal ICs, and W2BI’s portable Micro Line Tester (MLT™). This newly introduced system can leverage cloud technology to support testing of LTE-M devices – while effectively lowering the cost of testing smart devices and IoT-based technologies during their development and production life cycles.

MWC provided a valuable forum for Advantest to connect with customers and potential customers to share our perspective on the future of test in the wireless space, and to obtain their thoughts about where IoT test is headed. By most indicators, the space is only going to continue heating up.

Recent market estimates project a whopping 29 billion connected devices by year 2022, and 18 billion connections targeted at wide-area and short-range IoT devices (Figure 1). If we are to capably accommodate this growth, it is critical that the industry address key issues currently challenging wide-area IoT device implementation, including:

• Lengthy certification process
• Complex cellular tests used to ensure Safe For Network (SFN) operations
• Expensive lab equipment for lab testing
• Non-scalability of test solutions
• Travel to remote sites to perform live network tests is costly and time consuming
• Lack of certification knowledge and experience by IoT device makers new to the market

Figure 1. Connected devices are expected to achieve a combined CAGR of 10% between 2016 and 2022. Ericsson Mobile Report November 2016

Some of these challenges can be tackled by simplifying conformance and certification processes, as well as eliminating duplicate tests across the test lifecycle of chips, modules and end products (e.g., wearables, alarm panels, telemetry, and smart homes). Others, however, will require a change in the way the tests are conducted.

W2BI’s new portable all-in-one Micro Line Tester (MLT) platform tackles many of these issues head-on with several key benefits (illustrated in Figure 2):

• A portable and expandable cloud-managed test platform that reduces time to market;
• Automation capabilities that have the domain knowledge built in, thus allowing developers to focus on their specific product requirements;
• Validated industry-standard automated tests downloadable over the cloud directly at the customer site, enabling device pre-certification while reducing travel and lab costs;
• Pre-defined device profiles to efficiently automate tests across multiple device types (modules, smartphones, IoT products, etc.) without having to customize and adapt tests for each;
• Ability to expand within a small footprint to adapt to 5G requirements.

Figure 2. W2BI’s portable MLT platform enables onsite testing of mobile devices, greatly reducing test times and costs.

The MLT platform is currently offered in three different modes:

Standalone – Used to conduct ad-hoc tests such as basic device operation, network connectivity, network aggression, data throughput, Voice-over-LTE (VoLTE), SMS, LTE to WiFi handover, and others. The target areas are mainly R&D development processes, and isolation and troubleshooting of post-release device issues.

Developer – Used to create test automation scripts across the network emulator components (radio, packet core, IMS, application server, etc.) and the devices under test, and to collect test metrics for use in analytics. Target areas are primarily QA processes, stress testing, and returns and repair processes.

Conformance – Used to perform automated conformance and certification tests for devices that need to be deployed on wireless networks in accordance with industry standards or operator-specific requirements. The target areas are mainly pre-certification tests, network safe tests, and conformance tests.

W2BI’s MLT platform is currently deployed at a US Tier-1 wireless operator, performing conformance tests on smartphones, and IoT modules and products. The Micro Line Tester is also undergoing multiple trials across test labs, module manufacturers and smartphone OEMs using both the standalone and developer modes. Shipment volume is expected to pick up toward the second half of 2017, when mobile operators begin fully deploying LTE-M and NarrowBand IoT (NB-IoT) on their networks.
As W2BI continues to develop new products that help to enable the growth of the mobile device market, expect to see technologies and products that address new protocols, including LTE-M and NB-IoT, called a game changer for the IoT industry because it extends LTE’s market reach. By allowing LTE to cost-effectively support lower data-rate applications, LTE-M is being touted as a good fit for low-power sensing and monitoring devices such as health and fitness wearables, utility meters, and vending machines, among others.

RF Test Requirements Driven by Emergent Package Integration

By Judy Davies, VP, Global Marketing Communications, Advantest Corp.

The many connected tasks we perform every day using advanced mobile products, such as smartphones, tablets and notebooks, are enabled by a somewhat dizzying array of wireless standards. These range from Long Term Evolution (LTE), LTE-Advanced, LTE-A Pro and LTE-M smartphone standards, to ZigBee, Bluetooth, GPS and Wireless Local Area Network (WLAN). The requirements and performance criteria for these wireless technologies differ according to their application – many of which revolve around the Internet of Things (IoT) – creating a host of technological challenges, including those surrounding packaging and test.

Before they’re packaged, assembled and shipped, RF-based system-on-chip (SoC) devices built on the current Third-Generation (3G) and Fourth-Generation (4G) LTE broadband standards are fully tested and characterized, as are both the RF and analog baseband transceivers employed in these applications. In addition, the Fifth-Generation (5G) standard is forthcoming, with its promise of new speed and capacity levels, lower latency and greater flexibility than LTE, but its new encoding technologies and chip structures will require new production, packaging and test technologies. The anticipated needs of next-generation wireless networks are in fact shaping the next generation of RF test equipment.

The proliferation of advanced packaging methodologies – e.g., fan-out wafer-level packaging (FOWLP), multichip packages (MCPs), through-silicon vias (TSVs), embedded passives and actives, and systems-in-package (SIPs) – also plays a key role in growing RF test requirements. While it’s not clear which of these package types will dominate going forward, they are all impacting how steps such as wafer sort, final test, packaging test, burn-in and others are performed.

Packaging integration is key

With respect to packaging for RF transceivers, as well as for RF chips in general, every RF device comprises a large number of passive components, such as capacitors and inductors, allowing its use as an end product. Therefore, packaging integration is essential to turning RF silicon into a device that can easily communicate with the antenna in the RF space. The three primary components of integrated packages are as follows:

1. Embedded passive devices – embedded passives are essential to making useful RF end products based on RF chips, and they are a key value-add provided by outsourced semiconductor and test (OSAT) houses.
2. Multiple standards – many standards are integrated into today’s mobile phone, so it’s critical to implement an RF set that can handle these various standards. Multi-purpose RF devices switch modes when the user switches location, which makes them more both complex and more challenging to test.
3. Multiple antennas – essential to ensuring that a device will work no matter how it is held by the user, multiple antennas are increasingly being employed within wireless products.

OSATs are competing with each other to unify all of these components into a viable RF package. Flexible, scalable automated test equipment (ATE) is a fundamental requirement for thorough testing of these devices. This includes both early die sort and final test once the peripherals and passives are attached within the integrated package. Regardless of the packaging technique, more rigorous functional test and more robust compliance test are essential – highlighting the importance of precision, capability and bandwidth in new equipment. Combining a tester-per-pin architecture – such as the Advantest V93000 platform – with massive parallelism is one approach to ensuring the high performance and high utilization chipmakers need to get their products to market more quickly, and at a lower test cost.

Lessons of evolution

Much discussion is under way with respect to how packaging impacts the way test cards are developed – similar to what happened with printed circuit boards (PCBs) a decade or so ago. Back then, board test was big business. Virtually every electronics company created its own PCBs, using its own components, and put them into widely available electronic products. Since then, the PCB chain has consolidated, with a small number of very large subcontract manufacturers putting out PCB assemblies.

Package integration also faces a similar major change – more and more technology is being integrated into a single piece of silicon. PCBs are becoming smaller and smaller, or being eliminated entirely, as in products like the Apple Watch. As this industry shift continues to evolve, the line between chip and package is blurring – particularly with more intelligence being put into the package (which was once merely a “dumb” housing for the circuitry). Competition for business between PCB load and assembly houses and OSATs is also on the rise. What will be chosen depends on whether the customer needs one-stop shopping, which OSATs claim they can provide, or if they’d prefer to tap more traditional PCB load/assembly providers for the board.

A clear winner in this space is chip-scale packaging—particularly, wafer-level chip scale packaging (WLP). The majority of the building blocks in today’s smartphones are WLPs. Eliminating the classic substrate and consolidating the flow of material into wafer-level scale allows two goals to be addressed in one step: miniaturization (making the package ultra-thin) and cost scaling—a key requirement for high-volume manufacturing.

Reducing costs through parallelism

Signal transmission and reception in 5G systems will also impact future test equipment requirements, which are further complicated by the projected billions of IoT devices with different types of sensors using low-power wireless links to connect to the internet. These sensors will be located all around us, letting us access, interact with and control our environment no matter where we are – at home, at work or in transit.

Current RF testing solutions, which typically require multiple cards and a separate calibration kit, employ a fan-out architecture with shared subsystem resources. This means that devices with multiple frequency paths are actually tested in serial within the device, rather than in true parallel test mode. It also means that only one RF standard at a time can be tested per site.

One new approach is Advantest’s V93000 channel card called Wave Scale RF that omits shared resources, condensing four independent RF subsystems into one integrated card with a high degree of parallelism – up to 192 ports for parallel testing of multiple RF device types. This removes the limitations placed on test speedup, cutting test times in half, and enabling device parallelism of 16, 32 or even higher. These cards, together with the complementary Wave Scale MX (for mixed-signal) cards, can simultaneously test multiple standards or multiple paths within each RF device, achieving both in-site parallelism and high multi-site efficiency. Devices can be tested two to three times faster than with other solutions – greatly reducing the cost of test. This is a key requirement for OEMs and fabless semiconductor companies that need to quickly bring RF-enabled devices to market in high volumes.

Wave Scale MX is optimized for analog IQ baseband applications and testing of high-speed DACs and ADCs. As with Wave Scale RF, it omits shared resources, delivering parallel, independent operation of all 32 instruments controlled by a hardware sequencer. This is critical for semiconductor and telecommunications chip leaders, who face a 10x reduction from what they sell into cell phones to what they can charge in the industrial area. From a security perspective, the key challenge is that the functionality must ensure safety, while data is directed into the right channel and properly authorized – thus, the security requirement is even higher than for phone line communication.

In fact, security is one of the biggest concerns about the IoT– silicon providers will be under tremendous pressures to guarantee that their products adhere to industry reference standards. Whether these standards will be as stringent as those adopted within the automotive and aerospace industries remains to be seen, but they will most certainly need to be stronger than consumer-grade standards.

These requirements further underscore the need to rigorously and robustly qualify and test devices, as well as manufacturers’ need to ensure long-term device reliability (based on user demand). This means that the pressure to deliver high-quality devices at the lowest possible investment cost will continue to mount, requiring methodology breakthrough and further justifying the need for advanced equipment that can fully leverage these changes in the RF device landscape. With the new Wave Scale card, OEMs can address their bottom-line manufacturing and test cost pressures while ensuring a solution is in place with the flexibility and headroom to accommodate the requirements of the future.

System-Level Test Essential for Fast-Growing Embedded NAND Market

By Ken Hanh Duc Lai, Marketing Director, Advantest America

The market for NAND flash memories is growing at a rapid pace, driven in large part by the massive demand for solid state drives (SSDs), which have replaced hard disk drives for many applications. According to Gartner, the SSD market will reach above 370 million units in 2020, and IC Insights forecasts that memory IC products will show the strongest growth rate through 2021 of the four major IC product categories (the others being logic, analog and microcomponents).

A significant portion of the SSD market is commanded by PC servers and clients used for big data storage applications. However, the mobile market comprising portable wireless devices like smartphones and tablet PCs is growing as well, with variations in form factor increasing to meet new market demands. Driven by these applications, mobile memory unit shipments are forecast to exceed 2 billion units by 2020. These include embedded multimedia cards (eMMC), embedded multi-chip packages (eMCP), MCP and raw NAND. In concert with this growth, the embedded NAND market is undergoing a shift in protocol usage. Embedded NAND is in 80 percent of the smartphones currently on the market, and while smartphones and tablets have typically used eMMCs to store information, a transition is under way from eMMC to Universal Flash Storage (UFS) as the future of flash memory (see Figure 1).

Figure 1. UFS has taken hold, and is expected to represent half the market for NAND flash SSDs by 2020. (Source: IHS Mobile and Embedded Memory Market Tracker Q4 2016)

The JEDEC-defined UFS mobile-centric storage standard addresses next-generation mobile performance and scalability, offering fast sequential read/write speeds with high random IOPS1, which are essential for mobile phones. (For SSDs, random IOPS numbers are primarily dependent upon the storage device’s internal controller and memory interface speeds.) One key value of UFS is its ability to leverage the strengths of several existing technologies in one standard: the low power consumption of eMMC; the MIPI interface standard, M-PHY and UniPro, for the interconnect layer; and the SCSI command set as the application protocol.

Devices based on UFS 2.0, the current version of the standard, offer the highest available performance of any SSD interface standard due to its separately dedicated read/write paths, which enable UFS to read and write simultaneously. At up to 1200 Megabytes per second (MB/s), UFS operates at twice the rate of Serial ATA (SATA) 3.0 and three times that of eMMC5.0. UFS also consumes less total power by processing tasks sooner and staying in standby mode longer. Figure 2 summarizes the key benefits of UFS standard.

Figure 2. UFS offers a number of benefits that make it a superior option for embedded storage in mobile devices. (Source: Universal Flash Storage Association)

UFS is here

Adoption of UFS in the U.S. has already begun, with most of the top 10 mobile handset OEMs using UFS memory for their flagship models. While this includes primarily high-end handsets at the moment, as the cost to implement UFS continues to decline, more and more mid-tier phones will incorporate UFS-based embedded NAND memory devices. Moreover, the ecosystem for UFS is already in place, with a range of vendors supporting the UFS interface, including makers of NAND flash, systems-on-chip (SoCs), operating systems, measurement tools, and testers optimized for high-volume manufacturing (HVM).

Major NAND makers and manufacturers of UFS and BGA2 SSDs have adopted system-level test (SLT) for production use. More than 50 testers overall have been installed since the second half of 2016 for system-level testing of UFS and BGA SSDs, and this number is expected to triple during 2017.

Flexible tester optimized for embedded NAND

Memory IC makers need a class of tester that specializes in SLT of these devices, while maintaining the reliability, low cost and high volume capabilities required for conventional memory testers. Advantest developed its T5851 system-level test (SLT) solution – part of the T5800 platform series – specifically to meet these needs, delivering cost-effective testing of UFS and BGA SSDs. Built with the same proven test architecture used in Advantest’s MPT3000 family of SSD protocol test solutions, the T5851 allows customers to minimize both their capital investments and deployment risks by using the same platform and FutureSuite™ software as other members of the T5800 product line.

The flexible T5851 tester is available in both production and engineering models, allowing the system to be used for reliability and qualification testing as well as test-program development or, when equipped with an automated component handler such as Advantest’s M6242, high-volume production. As a fully integrated SLT solution, the T5851 provides multi-protocol support in one tool while its tester-per-DUT [device under test] architecture and proprietary hardware accelerator allow it to achieve industry-leading test times.

Currently, Advantest has many T5851 systems installed at IDM3 and OSAT4 customer sites worldwide for HVM production, qualification and engineering. This number is expected to increase as adoption of UFS becomes more widespread. This will be spurred by the release of UFS 3.0, as well as expansion of the standard into other applications, such as memory cards, PC clients, smart TVs, and automotive devices, which are anticipated to be the next emerging market for UFS. Advantest, as always, is working with its customers to stay on top of these developments to ensure its testers are future-ready to accommodate new requirements as they arise.

Notes:
IOPS = input/output operations per second
BGA = ball grid array
IDM = integrated device manufacturer
OSAT = outsourced semiconductor assembly and test

Interview with Ricky Sim

Q&A Interviewee
Ricky Sim, CEO & Managing Director, Advantest Singapore
By GO SEMI & Beyond staff

Singapore is home to the world’s top 3 wafer foundries, 30 major IC design centers, and offices for most of the leading fabless chipmakers and outsourced semiconductor assembly and test suppliers (OSATS). Similarly, six out of the world’s 10 largest semiconductor companies now have a presence in Malaysia. To learn more about the business environment in this region, we talked with Advantest Singapore CEO and Managing Director, Ricky Sim, who also shared his vision for the company going forward.

What do you see as the key factors driving the semiconductor industry growth in the Singapore/Malaysia region?

There is a combination of factors impacting the pace of growth here:

• The stable political environment and pro-business government policies to attract foreign investments and R&D efforts, including IP protection, definitely help. There is government support with taxes and other incentives to develop the semiconductor and electronics manufacturing ecosystem in the region.
• A ready and stable infrastructure, e.g., utilities, transportation, logistics and more.
• Access to a broad talent pool and a competitive workforce. This allows for a high degree of productivity.
• Availability of engineers, production operators, supervisors, first- and middle-level managers and senior managers – essentially, availability of talent at a reasonable cost to maintain competitiveness.
• Communication is relatively straightforward. English is the common business language, and some are also conversant in a second language, typically Mandarin or Malay. It is fairly simple for foreigners to operate in Singapore and Malaysia and, likewise, for people here to reach out to the other countries in the region.
• Both Singapore and Malaysia are strategically located in the South Asia Pacific region, with easy access to major markets and consumer insights.
• The massive growth in the Internet of Things (IoT) has helped to spur the demand for memory, wireless, microcontroller units and automotive electronics. The major players have a base in this region, and they can continue to benefit from this growth.

What needs to happen for this growth to continue?

First, global consumption must increase. The semiconductor business is very much a global business, so the major players have global presence and reach. Second, the value-add in terms of engineering content and productivity must increase. Smart integrated factories, production automation, R&D contributions and engineering value-add will be important.

Critical success factors will be the talent pool and collaborations between businesses and government agencies. The education system must attract and train young talents, and ensure that the talented individuals coming from universities and other higher education institutions have the relevant knowledge and skills to support the growth.
What impact do you believe developments in other regions, e.g., the U.K. “Brexit,” the new U.S. administration, etc., will have on the electronics business in Singapore & Malaysia?

It is still too early to tell the actual impact. This is a global business. Any uncertainties will, of course, create concerns regarding the economic outlook. Protectionist sentiments may hinder foreign direct investment (FDI) and transfer of intellectual capital. Should additional tariffs be imposed on imports, it may impact margins and/or consumption. In turn, this will place added pressure on the entire supply chain. Generally, any decisions or policies that hamper free trade and retard economic growth will impact business negatively. To mitigate the risks, governments are already working on alternative trade deals to forge forward.

How has Advantest Singapore grown in the region, and what role does it need to play going forward?

To sustain our growth in this region, we must focus on customers and their needs, and support their strategies. Knowledge transfer, productivity gain and cost optimization efforts will be instrumental. We need to anticipate trends and prepare for them in advance. We will work with customers and agencies to train and build up the talent pool while strengthening our internal processes across the regions and preparing our people to anticipate needs and to support growth.

What is your overall vision for Advantest Singapore? What growth goals for the business do you have that you can share?

Our key goals are to grow with our customers and grow multi-dimensionally. It will be essential to continually upgrade our skills, learn new technologies, build up our expertise and expand our coverage in the region.

Beyond the customer team, Advantest Singapore houses other global functions, and we look forward to leveraging the respective functional experts to support corporate initiatives and help make Advantest an even greater company!

Enabling High-Volume Optical and Electrical Test on 100Gbps Optical Interconnect Devices

By Tasuku Fujibe, Consulting Manager, and Hiroyuki Mineo, Senior Engineer, Advantest

High-speed data communications demand is rising at astronomical rates. According to a forecast from Cisco Systems, the volume of global data center traffic is expected to increase to more than 10 zettabytes per year in 2019. In response, new network architectures are being considered, while data centers are being housed in much larger buildings. As this requires interconnection devices (switches, routers, etc.) to support distances of as much as several kilometers, using electrical interconnection devices in these very large data centers is becoming impractical. Moving forward, optical interconnection devices will need to be implemented in high volumes, creating new test challenges. Currently, rack-and-stack solutions are used to test these devices, but new manufacturing approaches are needed to avoid the bottlenecks such approaches can create.

To answer this demand, Advantest has developed a test solution with the ability to cover high-speed interconnection devices, both electrical and optical – particularly those destined for high-speed datacom applications. Designed for high-volume manufacturing, the T2000 scalable test platform can be configured to test current digital signal processors (DSPs) as well as high-speed buses and communication interfaces due to its modular architecture.

Platform offers high flexibility

The T2000 ATE solution consists of a high-speed optical/electrical test module, a low-speed digital module for I2C ports, and a device power supply module (Figure 1), all of which are integrated into the test platform. The test module’s 64 ports can operate up to 28 Gigabits per second (Gbps). This includes 32 optical ports – 16 transmit (TX) and 16 receive (RX) – and 32 differential electrical ports (16 TX and 16 RX). The T2000 platform also includes high-performance device fixture technology for both the optical and electrical ports to perform device interface.

To understand the benefits the T2000 platform enables, let’s take a closer look at the device fixture and the high speed optical/electrical test module.

Device fixture and test module

The device fixture provides both optical and electrical signal connections between the device-under-test (DUT) and the test module. To test optical lanes, the device fixture must support such optical assemblies as MT-connectors. However, ordinary MT-connectors have a limited insertion lifetime (typically, less than 300 insertions), making them inappropriate for this application. To overcome this limitation, Advantest has developed a high-volume-capable non-contacting optical connector that is fully compatible with MT-connectors.

Figure 2 shows the new optical connector and illustrates the approach used for its fabrication. Using a gradient-index (GRIN) lens to maintain a working distance of 150 microns (µm) enabled development of a high-performance optical connection with no physical contact between the end of the fiber-optic cable and the connector.  Because the new connector is MT-connector-compatible, it can be used to make contact with MPO connectors, which are typically used in compact QSFP+ PSM4 transceivers used for data communications.

The high-speed optical port block diagram is shown in Figure 3. FUNC ASIC has pattern generator (PG) and bit error rate tester (BERT) functionalities, both of which can operate up to 28 Gbps. For electrical ports, the FUNC ASIC is connected to the DUT via the device fixture. For optical ports, the output test signal from FUNC ASIC goes to the optical modulator to modulate the continuous wave laser provided by the laser source. Variable optical attenuators (VOAs) adjust output power to the DUT to test the DUT’s receiver sensitivity. The optical signal provided to the DUT is connected to a photo detector and trans-impedance amplifier (TIA) in the test module to convert it to an electrical 28-Gbps signal. Then FUNC ASIC captures the signal to measure eye diagram by using its BERT capability.

Measurement results

During device fixture evaluation, insertion loss variation was measured against iterations. The results, seen in Figure 4, showed stable insertion loss variation of less than +/-0.3 dB during 100,000 repeated operations. Compared to ordinary MT-connectors, which have an anticipated lifetime of less than 300 cycles, this connector can provide stable measurement with a longer lifecycle.

Current 100-Gbps datacom transceiver interfaces, such as PSM4, CLR4 or CWDM4, use four lanes of both optical and electrical 25-Gbps lanes to achieve aggregated band width of 100-Gbps. The test module has 16 lanes of both optical and electrical high speed ports. The scalable platform can simultaneously test four DUTs per optical port module; integrating two modules onto a test solution thus allows parallel test of up to eight DUTs. Multi-site testing increases system throughput and significantly drops per-site equipment costs.

Summary

The semiconductor industry roadmap for optical transceivers – advanced semiconductor devices that transmit and receive data through optical fibers – calls for boosting speeds from today’s 40-Gbps interconnections to as much as 400-Gbps by 2020. Advantest’s T2000 solution is among the first integrated solutions able to cost-efficiently test these high-speed devices.

Since typical 100G transceivers use four 25-Gbps ports to achieve aggregated bandwidth of 100-Gbps, the T2000 configuration allows four 100-Gbps devices to be tested simultaneously, improving test throughput and reducing system cost. It also includes a device fixture solution that provides stable and longer-lifecycle non-contacting optical connectors, making the system well suited for high-volume manufacturing environments.

Find out more:

IoT Devices Require a New DFT Paradigm and Scalable ATE

By Neils Poulsen, Director of SoC Business Development, Advantest

Touted as the “next big thing” to drive the next major wave of semiconductor device growth, the emerging market for the Internet of Things (IoT) is widely projected to increase semiconductor device volumes by tens of billions of units over the next several years. These volumes will be fueled by myriad new consumer end-user applications and services, to be provided by hundreds of companies ranging widely in size and resources.

IoT devices comprise several functions: computation (typically a microcontroller); communication (typically a wireless/radio frequency [RF] connection); and multiple sensors and/or actuators, the quantity of which depends on the end-use application. Sensors are used to detect environmental parameters, such as temperature, acceleration, magnetic field, moisture, light intensity or distance. The received signals are processed via integrated microcontroller or DSP cores, and the information is passed on to wireless devices via wireless communication interfaces. The integrated cores’ performance is significant, as data encryption is often required due to security aspects in IoT products. Other key functional components in smart devices are drivers for actuators to convert electrical signals into movements. Typically, these are integrated driver circuits for brushless DC motors or relay drivers.

Because these devices must operate on small batteries for extended periods of time – sometimes years – they must be able to consume very low amounts of power. Bluetooth Low Energy, ZigBee, WiFi and other communications standards are designed for low power requirements and optimized for easy network integration. This combination of requirements presents many challenges to designers and test engineers, as these complex devices are increasingly becoming more like high-end systems-on-chip (SoCs), but necessarily sell at a small fraction of the price.   

Moreover, the dynamic nature of the consumer market, as well as the large number of competing companies, is placing tremendous pressure on semiconductor suppliers to shorten both their time to market (TTM) and time to quality (TTQ). Improving these parameters will allow them to secure customer design wins and achieve the necessary volumes and quality levels their customers require – at the same time, meeting their own cost targets, including acceptable manufacturing yields (see Figure 1).

Figure 1

To profitably compete in the IoT market, companies must find ways to significantly increase their overall efficiency and reduce their overall costs. This means they must consider breaking away from their traditional approaches and embrace a new paradigm for the design-to-manufacturing process, including test.

Changing the paradigm

In the traditional process flow (Figure 2), design and DFT (design-for-test) engineers use test instrumentation in benchtop setups during initial device bring-up to debug and verify the chip’s proper operation. This includes building special fixturing to interface the device-under-test (DUT) to various multiple instruments, as well as translating patterns from the design simulation environment into test vectors that can execute in the benchtop instruments to control and stimulate the DUT. To test complex IoT chips’ complete functionality (i.e., digital, analog and RF) as they become more integrated, these engineers typically write time-consuming custom software routines to control and coordinate multiple benchtop instruments.

Figure 2

Similarly, in the next step of the traditional process, the characterization phase, engineers typically use benchtop instrumentation to evaluate the chip’s performance, validate specifications, and determine operating margins across a range of operating conditions, including frequency, voltage and current. This can be a time-consuming, manual process. In addition, the instrumentation, device fixturing and custom software routines usually differ from those used in the design verification phase. This leads to inefficient duplication of engineering resources and can create delays in the overall process.

To garner a statistically valid sample, many devices should be characterized, but collecting and analyzing the large amount of data needed to do this is limited by the slow throughput and difficulty of interfacing bench setups to automated device handlers. As a result, because of TTM pressures, only a few devices usually receive this high level of characterization, and the range of operating conditions is limited, which can negatively impact quality and device yields later during the manufacturing process. This is also typically the phase when customer samples are first provided, based on characterization data, so time-consuming benchtop characterization limits the number of sample devices that can be shipped to customers, which can limit market potential.    

In the next phase of the traditional process, test engineers develop test programs on ATE that will be used to test the devices in high-volume manufacturing (HVM). However, the ATE instrumentation, DUT fixturing and software environment are all very different than the bench set-ups. This means there is very little compatibility between the earlier Design Verification and Characterization phases and the HVM Test Program Development phase. Once again, this results in duplication of engineering effort, including designing new DUT interface fixturing, performing additional ATE characterization to correlate to the benchtop characterization data, and determining test limit guard-bands to ensure HVM test quality. The different environments also mean that correlating the HVM test results to the benchtop data can be difficult and time consuming, requiring multiple iterations and further delaying TTQ.

Implementing a new approach

A new integrated ATE solution being embraced by several leading semiconductor suppliers utilizes engineering ATE that comprises the same hardware instrumentation, software environment and DUT interface fixturing as the ATE used for HVM test (Figure 3).  This compatibility accelerates test program development and bring-up, correlation and release to HVM by leveraging the engineering efforts from the previous phases – resulting in reduced costs and improved TTQ.

Figure 3

Design/DFT engineers can utilize low-cost engineering ATE for their initial device debug and verification so that when they translate their simulation patterns to test vectors, these same vectors can be used by test engineers for their HVM test program. This eliminates redundant vector translation, enables test engineers to begin test program development earlier, and minimizes problems and delays due to revision errors.

Similarly, by combining low-cost ATE with a cost-effective engineering handler, an automated “production-like” environment and high-throughput characterization test programs, engineers can realistically characterize thousands of engineering samples in far less time, significantly reducing TTM. And by collecting and analyzing much more data over a far wider spectrum of operating conditions, they can significantly increase quality.

Advantest V93000 platform handles multiple requirements

Advantest is enabling this integrated test approach via its V93000 platform of testers, which includes the scalable A-Class configuration. A cost-effective engineering ATE solution, the A-Class uses the same hardware instrumentation, software and DUT interface fixturing as the other members of the V93000 family (see Figure 4), facilitating transition across the V93000 platform as needed. This includes high-density instruments that utilize the universal pin concept (every pin can generate and receive the digital, analog or RF signals needed to test IoT devices).

Figure 4

Utilizing the V93000 A-Class in engineering for design verification and characterization creates a seamless streamlined process, in which:

• Performing the initial device debug and bring-up on the same DUT fixturing that will be used in HVM enables removing the loadboard from the critical path;
• Reusing common test routines speeds up the entire DV-to-HVM process and can result in having the HVM test program complete with first customer samples; and
• Automated high throughput characterization (in conjunction with an engineering handler) provides faster and higher-volume data collection, on a significantly larger number of devices.

Implementing the Wave Scale RF channel card makes the V93000 A-Class even more effective as an economical engineering option for the IoT market. Wave Scale RF was designed with four independent subsystems per board to eliminate shared pin resources. This enables both in-site and high multi-site parallel testing, helping achieve test time reductions of up to 50 percent or more, compared to traditional RF architectures.

Through the combination of all these capabilities that allow users to conduct their engineering activities on the same platform and instrumentation set that they use for high-volume production, Advantest has developed a scalable solution that improves engineering efficiency, lowers overall costs, reduces TTM and improves TTQ – helping semiconductor suppliers to compete in the emerging IoT market.

Find out more: