Storage Evolution Driving Growth of System-Level Test

By Colin Ritchie, Vice President, System Level Test Business Unit, Advantest,
and Scott West, Marketing Manager, System Level Test Business Unit, Advantest

Thanks in large part to the booming mobile market, global demand for storage capacity continues unabated. Gartner indicates that solid-state drive (SSD) shipments are on pace to top 370 million units by 2020, while Research & Markets forecasts that the client SSD market alone will grow at a compound annual rate (CAGR) of 36 percent between 2017 and 2021. With this growth comes an increased drive for performance, requiring implementation of new/updated storage protocols.

Currently, the market supports three primary storage protocols. Serial ATA (SATA) and Serial Attached SCSI (SAS) are still in use – the latter, for enterprise applications in particular – but there is a migration towards the newer PCI Express protocol. Increasingly, SSD makers are choosing the latest incarnations of PCI Express: PCIe Gen 3 and the forthcoming Gen 4. In addition, often used with PCIe is Non-Volatile Memory Express (NVMe), a storage interface/protocol developed especially for SSDs by a consortium of prominent vendors.

This shift toward newer, faster protocols creates an associated need for improved test speed and accuracy. Driven by these and other associated demands, the test industry is moving up the value chain, from component-level to module-level to system-level testing. System-level test (SLT) is not only different from classical component test, but also more difficult, creating some key challenges to be addressed.

In-house solutions no longer viable

Storage SLT is still in its infancy, much as memory test was three decades ago. However, an SSD’s state machine has virtually an infinite number of combinations that must be tested effectively without an infinite amount of time available to perform brute-force iterations. While ICs have a set number of vectors or memory patterns to be run, SSDs feature a huge number of constantly changing states – factor in unplanned events (such as power-cycling), and the result is a huge number of cases that are difficult to cover. SSD providers can’t address every eventuality – but they must be able to ship product to their customers with absolute confidence it will work.

Traditionally, storage makers have created their own test solutions in-house because of the high degree of customization required – in addition, no commercially viable solution was available that could meet their needs. However, as the pace of change and growth in the storage market continue to accelerate, these companies have come to recognize that they cannot keep developing their own internal test solutions – they will end up spending more time, money and engineering resources on developing the ability to test their products than they will on developing the actual products. Greater expertise is needed to test the higher performance devices while maintaining a consistent solution across increasing production volumes is. Faster product cycles make this an even more pressing issue.

SSD product lifecycles have collapsed down from two years to as little as six months. In the time it would take for a storage maker to develop its own custom test solution, the product for which it’s intended will have already peaked and be on its way to obsolescence. Reinventing the wheel with each new product is simply no longer viable. Most of these manufacturers have thus made the decision to implement commercial test solutions.

Advantest leading the way in SLT

This creates a substantial opportunity for Advantest. Storage is a market in which Advantest has purposely become a fundamental enabler of growth, as well as a quality arbitrator. The company is committed to helping customers wean themselves away from in-house-developed test solution, with its MPT3000 platform allowing customers to focus on their core competencies. As an example, an executive with a leading SSD supplier that previously focused on traditional flash memory components, recently acknowledged his company’s decision to align itself with Advantest. They needed a partner they could depend on to develop the volume of test solutions needed to meet customer demand in the face of collapsing time-to-market (TTM) windows.

The platform strategy Advantest has refined in the ATE industry applies directly to system level test. By developing modular components for the common platform, both standard solutions as well as targeted custom solutions can be configured, cost effectively. When a custom need arises, the platform components provide 80 to 90 percent of the solution, allowing efficient use of Advantest’s expertise to adapt the solution to a specific configuration. Each adaptation extends the platform so storage makers can benefit, through working with Advantest, from their peers’ shared knowledge and experience.

Going back to the shortened product lifecycle, when the TTM window is only six to nine months, missing one design win can greatly impact a storage maker’s business. A three-month delay in the product cycle can translate to a 10-percent market-share hit – e.g., a loss of $100 million from a $1 billion SSD revenue stream is clearly significant! Advantest’s goal is to take test off the table for customers when competing for business – the tester should never be a gating factor in this regard. By implementing the modular MPT3000 platform, they can compete on their product differentiation

Another key challenge storage makers face is of the need for flexibility in terms of manufacturing floor configuration. They spend significant amounts of money building their factories based on their business forecast, customer demand and production plan. However, as we’re seeing increasingly, these plans can change dramatically in a short time, necessitating flexible solutions on their factory floor that can be retooled easily, efficiently and cost-effectively to meet changing customer demand and/or when moving from one product generation to the next. The MPT3000’s FPGA-based test architecture enables quick changeover, maximizing utilization and production output for customers.

Advantest’s portfolio today comprises end-to-end test – from components through modules to systems. The MPT3000 platform is focused on system-level test for the SSD market, and is serving as both a test case, if you will, and a learning platform for further SLT efforts within the company. A previous GO SEMI article delved further into its protocol test capabilities: http://www.gosemiandbeyond.com/applying-flexible-ate-technology-to-protocol-test-and-the-ssd-market/

Other past articles that shed light on Advantest’s system-level test efforts include last issue’s piece on SLT for embedded NAND flash memories – http://www.gosemiandbeyond.com/system-level-test-essential-for-fast-growing-embedded-nand-market/ – and a prior interview with Artun Kutchuk of Advantest Group’s W2BI business, which provides wireless test automation products for the mobile and IoT space: http://www.gosemiandbeyond.com/out-of-the-lab-and-into-the-field-making-iot-device-testing-portable/.

We are interested in learning about the kinds of SLT challenges you face – whether in storage or elsewhere. Please feel free to comment below, or send an email to Scott.West@Advantest.com, to share your knowledge and expertise.

A Smarter SmarTest: ATE Software for the Next Generation of Electronics

By Rainer Donners, Product Manager, Advantest Corp.

The complexity of the ICs being designed into consumer and communications devices continues to increase. The 10-nanometer (nm) node is here, and some chipmakers are already beginning to turn out 7-nm devices. With smaller transistors that pack more and more functionality on a single chip, the complexity of test programs is increasing apace with that of the ICs themselves.

These ICs are used in end products such as smartphones, Internet of Things (IoT) devices, computer and gaming products, and they are ‘multi-domain,’ i.e., they contain digital, DC, analog and radio-frequency (RF) circuitry all on the same chip. Developing efficient test programs for these multi-domain ICs within a shorter time to market (TTM) is becoming a challenge.

To overcome this challenge, Advantest has introduced SmarTest 8, the latest version of its SmarTest software, developed to support the V93000 test platform. It’s important to note that both SmarTest 8 and SmarTest 7 will coexist on the V93000 Series for the next decade, enabling customers to use the version best suited to their test needs and business requirements. SmarTest 8 works with all V93000 Series test cards introduced since 2011; see Figure 1 for cards supported by SmarTest 8.

Figure 1. V93000 Cards supported with SmarTest 8

SmarTest 8 features a host of new capabilities that will enable engineers who must deal with highly complex test programs to achieve superior parallelism and throughput. The new software’s many benefits include:

• Faster test program development
• Efficient debug and characterization
• Higher throughput, earlier, due to automated optimization
• Faster time to market
• Ease of test-block reuse
• Efficient collaboration

SmarTest 8 unifies multiple different tools within the SmarTest Work Center (SWC) environment, delivering a state-of-the-art look and feel and an entirely new design to ensure ease of use; see Figure 2.  Let’s take a look at some of the key SmarTest 8 concepts, features and tools that will allow users to reap the new product’s benefits for their test programs.

Figure 2. SmarTest 8 comprises a suite of tools designed to simplify and optimize test program development and debug

Operating Sequence
Advanced multi-domain devices consist of multiple different functional blocks. Typical block types include an RF block for transmitting/receiving phone signals, a protocol-ware (PA) interface to condition the device, analog blocks for microphone use and playing music, and/or digital blocks for processing.

Testing one functional block, e.g. the RF block, typically requires ‘assembling a test’ out of multiple pieces, e.g., starting an analog stimulus signal, conditioning the device with digital signals, and starting one or multiple RF measurements. Figure 3 provides an example, with three RF tests displayed in the Operating Sequence View.

Figure 3. Operating Sequence View, displaying an example RF test

The Operating Sequence is designed to easily assemble the multiple ‘test pieces,’ with precise synchronization where needed. These test pieces are typically patterns, protocol transactions, or ‘actions.’ Actions can be DC stimulus changes (e.g., stepping up a ramp), DC measurements, analog stimulus and measurements, or RF stimulus and measurements – to name some examples.

In addition to easy test setup, the Operating Sequence supports intuitive debugging; the screen view in Figure 3 displays exactly what has been executed.  Interactive changes during debug are well supported – as the second blue block in the figure indicates, inserting an additional transaction into one PA block changes the length of this conditioning block. The SmarTest 8 software automatically ensures that with the next execution of this test, subsequent actions (like cw2 and measurePower in the screen view) are shifted and retain their synchronous start.

Additionally, the Operating Sequence contributes to fast throughput. Multiple measurements can run in parallel, per Figure 3, in which two RF ports are tested concurrently. In addition, the execution of an Operating Sequence is done entirely via the unique test-processor-per-pin hardware of the V93000 system. No software or workstation interaction is required.

Overall, the Operating Sequence, with its new functionality, ease-of-use and optimal throughput, helps enable shorter TTM. This unique tool and concept are unavailable in competitive offerings.

Modular Test Program Structure
Test programs are complex, consisting of up to multiple thousands of tests for the different blocks of the device. The structure of the test setup data of SmarTest 8 is designed to easily deal with this complexity: SmarTest 8 incorporates the concept of subflows. Subflows as part of the testflow tool are established in the ATE software already. SmarTest 8 adds the new component that setup data can be structured and stored in separate and independent ‘subflow’ directories.

This capability enables multiple unique advantages:

• Teams can work on their own subflows independent from other teams, so collaboration is easy.
• No manual ‘merge’ effort is needed, as merging of the subflows is automatically performed by SmarTest 8.
• A complete (proven, debugged) subflow can be reused within multiple test programs of a device family. Reuse here refers to one single source of the subflow, not the ‘copy/paste’ approach typically used today. The latter creates test program maintenance challenges that are prevented with SmarTest 8’s re-use/single-source approach.

By making development and debug faster, easier and far less complex, the modular test program structure ultimately contributes to reduced TTM and time to quality (TTQ).

Test-oriented Use Model via Instruments
Many test systems’ use model is tester- or hardware-centric – it requires the user to learn how to program the tester in order to achieve the needed tasks. SmarTest 8 moves away from this model, allowing the user to focus on the test, not the tester.

With SmarTest 8, the user ‘thinks’ in terms of using instruments for his/her test tasks. Figure 4 shows example instruments and their respective implementations of the tester hardware cards.

Figure 4. Simplified use model via SmarTest 8 Instruments

These instruments are then programmed via properties and actions; see Figure 5 for an example setup for two VCC signals.

Figure 5. Level specifications for VDDA and VDDD signals

This level specification is identical for all DC instruments in SmarTest 8. When setting up the test, the test engineer will use the level specification for all suitable hardware, which could be a DC Scale DPS128, a parametric measurement unit (PMU) of a Pin Scale 1600 or a PMU of a Wave Scale MX card.

This test-orientation and tester, respectively, hardware-abstraction is consequently used in SmarTest 8, for test setup descriptions, application programming interfaces (APIs), access to results, and in debug tools. This makes the software intuitive and easy to learn, and the test programs are easy to develop, understand and debug, further lightening the burden for the test engineer.

In summary, after several years of development, optimization and beta test, SmarTest 8 is now ‘ready for prime time.’ It is installed at numerous customers, both in test program development and in high- volume manufacturing. SmarTest 8 delivers new benefits that, together with the proven V93000 platform, meets the test needs for the next/newest generation of advanced multi-domain, multi-core ICs. As part of the V93000 platform, it will be continuously expanded to enable even more capabilities and to make test engineers more efficient.

W2BI in the Spotlight at Mobile World Congress with New Test Automation Products for the Wireless Market

Advantest, together with W2BI ‒ an Advantest Group company that provides test automation products to help customers quickly launch high-quality smart devices ‒ showcased their newest test platforms for the wireless electronics market at the 2017 Mobile World Congress (MWC) in Barcelona, Spain.

The world’s most expansive exhibition for wireless technology and mobile devices, MWC serves as an annual springboard for many of the next year’s biggest announcements and rollouts of smartphones, tablets and other connected devices. To give you an idea of scale, MWC this year drew more than 108,000 attendees from 208 different countries and boasted approximately 2,300 exhibiting companies.

Within its booth, Advantest featured a suite of products for the mobile communications and Internet of Things (IoT) markets. This included the EVA100 tester, designed for highly efficient evaluation and measurement of analog/mixed-signal ICs, and W2BI’s portable Micro Line Tester (MLT™). This newly introduced system can leverage cloud technology to support testing of LTE-M devices – while effectively lowering the cost of testing smart devices and IoT-based technologies during their development and production life cycles.

MWC provided a valuable forum for Advantest to connect with customers and potential customers to share our perspective on the future of test in the wireless space, and to obtain their thoughts about where IoT test is headed. By most indicators, the space is only going to continue heating up.

Recent market estimates project a whopping 29 billion connected devices by year 2022, and 18 billion connections targeted at wide-area and short-range IoT devices (Figure 1). If we are to capably accommodate this growth, it is critical that the industry address key issues currently challenging wide-area IoT device implementation, including:

• Lengthy certification process
• Complex cellular tests used to ensure Safe For Network (SFN) operations
• Expensive lab equipment for lab testing
• Non-scalability of test solutions
• Travel to remote sites to perform live network tests is costly and time consuming
• Lack of certification knowledge and experience by IoT device makers new to the market

Figure 1. Connected devices are expected to achieve a combined CAGR of 10% between 2016 and 2022. Ericsson Mobile Report November 2016

Some of these challenges can be tackled by simplifying conformance and certification processes, as well as eliminating duplicate tests across the test lifecycle of chips, modules and end products (e.g., wearables, alarm panels, telemetry, and smart homes). Others, however, will require a change in the way the tests are conducted.

W2BI’s new portable all-in-one Micro Line Tester (MLT) platform tackles many of these issues head-on with several key benefits (illustrated in Figure 2):

• A portable and expandable cloud-managed test platform that reduces time to market;
• Automation capabilities that have the domain knowledge built in, thus allowing developers to focus on their specific product requirements;
• Validated industry-standard automated tests downloadable over the cloud directly at the customer site, enabling device pre-certification while reducing travel and lab costs;
• Pre-defined device profiles to efficiently automate tests across multiple device types (modules, smartphones, IoT products, etc.) without having to customize and adapt tests for each;
• Ability to expand within a small footprint to adapt to 5G requirements.

Figure 2. W2BI’s portable MLT platform enables onsite testing of mobile devices, greatly reducing test times and costs.

The MLT platform is currently offered in three different modes:

Standalone – Used to conduct ad-hoc tests such as basic device operation, network connectivity, network aggression, data throughput, Voice-over-LTE (VoLTE), SMS, LTE to WiFi handover, and others. The target areas are mainly R&D development processes, and isolation and troubleshooting of post-release device issues.

Developer – Used to create test automation scripts across the network emulator components (radio, packet core, IMS, application server, etc.) and the devices under test, and to collect test metrics for use in analytics. Target areas are primarily QA processes, stress testing, and returns and repair processes.

Conformance – Used to perform automated conformance and certification tests for devices that need to be deployed on wireless networks in accordance with industry standards or operator-specific requirements. The target areas are mainly pre-certification tests, network safe tests, and conformance tests.

W2BI’s MLT platform is currently deployed at a US Tier-1 wireless operator, performing conformance tests on smartphones, and IoT modules and products. The Micro Line Tester is also undergoing multiple trials across test labs, module manufacturers and smartphone OEMs using both the standalone and developer modes. Shipment volume is expected to pick up toward the second half of 2017, when mobile operators begin fully deploying LTE-M and NarrowBand IoT (NB-IoT) on their networks.
As W2BI continues to develop new products that help to enable the growth of the mobile device market, expect to see technologies and products that address new protocols, including LTE-M and NB-IoT, called a game changer for the IoT industry because it extends LTE’s market reach. By allowing LTE to cost-effectively support lower data-rate applications, LTE-M is being touted as a good fit for low-power sensing and monitoring devices such as health and fitness wearables, utility meters, and vending machines, among others.

RF Test Requirements Driven by Emergent Package Integration

By Judy Davies, VP, Global Marketing Communications, Advantest Corp.

The many connected tasks we perform every day using advanced mobile products, such as smartphones, tablets and notebooks, are enabled by a somewhat dizzying array of wireless standards. These range from Long Term Evolution (LTE), LTE-Advanced, LTE-A Pro and LTE-M smartphone standards, to ZigBee, Bluetooth, GPS and Wireless Local Area Network (WLAN). The requirements and performance criteria for these wireless technologies differ according to their application – many of which revolve around the Internet of Things (IoT) – creating a host of technological challenges, including those surrounding packaging and test.

Before they’re packaged, assembled and shipped, RF-based system-on-chip (SoC) devices built on the current Third-Generation (3G) and Fourth-Generation (4G) LTE broadband standards are fully tested and characterized, as are both the RF and analog baseband transceivers employed in these applications. In addition, the Fifth-Generation (5G) standard is forthcoming, with its promise of new speed and capacity levels, lower latency and greater flexibility than LTE, but its new encoding technologies and chip structures will require new production, packaging and test technologies. The anticipated needs of next-generation wireless networks are in fact shaping the next generation of RF test equipment.

The proliferation of advanced packaging methodologies – e.g., fan-out wafer-level packaging (FOWLP), multichip packages (MCPs), through-silicon vias (TSVs), embedded passives and actives, and systems-in-package (SIPs) – also plays a key role in growing RF test requirements. While it’s not clear which of these package types will dominate going forward, they are all impacting how steps such as wafer sort, final test, packaging test, burn-in and others are performed.

Packaging integration is key

With respect to packaging for RF transceivers, as well as for RF chips in general, every RF device comprises a large number of passive components, such as capacitors and inductors, allowing its use as an end product. Therefore, packaging integration is essential to turning RF silicon into a device that can easily communicate with the antenna in the RF space. The three primary components of integrated packages are as follows:

1. Embedded passive devices – embedded passives are essential to making useful RF end products based on RF chips, and they are a key value-add provided by outsourced semiconductor and test (OSAT) houses.
2. Multiple standards – many standards are integrated into today’s mobile phone, so it’s critical to implement an RF set that can handle these various standards. Multi-purpose RF devices switch modes when the user switches location, which makes them more both complex and more challenging to test.
3. Multiple antennas – essential to ensuring that a device will work no matter how it is held by the user, multiple antennas are increasingly being employed within wireless products.

OSATs are competing with each other to unify all of these components into a viable RF package. Flexible, scalable automated test equipment (ATE) is a fundamental requirement for thorough testing of these devices. This includes both early die sort and final test once the peripherals and passives are attached within the integrated package. Regardless of the packaging technique, more rigorous functional test and more robust compliance test are essential – highlighting the importance of precision, capability and bandwidth in new equipment. Combining a tester-per-pin architecture – such as the Advantest V93000 platform – with massive parallelism is one approach to ensuring the high performance and high utilization chipmakers need to get their products to market more quickly, and at a lower test cost.

Lessons of evolution

Much discussion is under way with respect to how packaging impacts the way test cards are developed – similar to what happened with printed circuit boards (PCBs) a decade or so ago. Back then, board test was big business. Virtually every electronics company created its own PCBs, using its own components, and put them into widely available electronic products. Since then, the PCB chain has consolidated, with a small number of very large subcontract manufacturers putting out PCB assemblies.

Package integration also faces a similar major change – more and more technology is being integrated into a single piece of silicon. PCBs are becoming smaller and smaller, or being eliminated entirely, as in products like the Apple Watch. As this industry shift continues to evolve, the line between chip and package is blurring – particularly with more intelligence being put into the package (which was once merely a “dumb” housing for the circuitry). Competition for business between PCB load and assembly houses and OSATs is also on the rise. What will be chosen depends on whether the customer needs one-stop shopping, which OSATs claim they can provide, or if they’d prefer to tap more traditional PCB load/assembly providers for the board.

A clear winner in this space is chip-scale packaging—particularly, wafer-level chip scale packaging (WLP). The majority of the building blocks in today’s smartphones are WLPs. Eliminating the classic substrate and consolidating the flow of material into wafer-level scale allows two goals to be addressed in one step: miniaturization (making the package ultra-thin) and cost scaling—a key requirement for high-volume manufacturing.

Reducing costs through parallelism

Signal transmission and reception in 5G systems will also impact future test equipment requirements, which are further complicated by the projected billions of IoT devices with different types of sensors using low-power wireless links to connect to the internet. These sensors will be located all around us, letting us access, interact with and control our environment no matter where we are – at home, at work or in transit.

Current RF testing solutions, which typically require multiple cards and a separate calibration kit, employ a fan-out architecture with shared subsystem resources. This means that devices with multiple frequency paths are actually tested in serial within the device, rather than in true parallel test mode. It also means that only one RF standard at a time can be tested per site.

One new approach is Advantest’s V93000 channel card called Wave Scale RF that omits shared resources, condensing four independent RF subsystems into one integrated card with a high degree of parallelism – up to 192 ports for parallel testing of multiple RF device types. This removes the limitations placed on test speedup, cutting test times in half, and enabling device parallelism of 16, 32 or even higher. These cards, together with the complementary Wave Scale MX (for mixed-signal) cards, can simultaneously test multiple standards or multiple paths within each RF device, achieving both in-site parallelism and high multi-site efficiency. Devices can be tested two to three times faster than with other solutions – greatly reducing the cost of test. This is a key requirement for OEMs and fabless semiconductor companies that need to quickly bring RF-enabled devices to market in high volumes.

Wave Scale MX is optimized for analog IQ baseband applications and testing of high-speed DACs and ADCs. As with Wave Scale RF, it omits shared resources, delivering parallel, independent operation of all 32 instruments controlled by a hardware sequencer. This is critical for semiconductor and telecommunications chip leaders, who face a 10x reduction from what they sell into cell phones to what they can charge in the industrial area. From a security perspective, the key challenge is that the functionality must ensure safety, while data is directed into the right channel and properly authorized – thus, the security requirement is even higher than for phone line communication.

In fact, security is one of the biggest concerns about the IoT– silicon providers will be under tremendous pressures to guarantee that their products adhere to industry reference standards. Whether these standards will be as stringent as those adopted within the automotive and aerospace industries remains to be seen, but they will most certainly need to be stronger than consumer-grade standards.

These requirements further underscore the need to rigorously and robustly qualify and test devices, as well as manufacturers’ need to ensure long-term device reliability (based on user demand). This means that the pressure to deliver high-quality devices at the lowest possible investment cost will continue to mount, requiring methodology breakthrough and further justifying the need for advanced equipment that can fully leverage these changes in the RF device landscape. With the new Wave Scale card, OEMs can address their bottom-line manufacturing and test cost pressures while ensuring a solution is in place with the flexibility and headroom to accommodate the requirements of the future.

System-Level Test Essential for Fast-Growing Embedded NAND Market

By Ken Hanh Duc Lai, Marketing Director, Advantest America

The market for NAND flash memories is growing at a rapid pace, driven in large part by the massive demand for solid state drives (SSDs), which have replaced hard disk drives for many applications. According to Gartner, the SSD market will reach above 370 million units in 2020, and IC Insights forecasts that memory IC products will show the strongest growth rate through 2021 of the four major IC product categories (the others being logic, analog and microcomponents).

A significant portion of the SSD market is commanded by PC servers and clients used for big data storage applications. However, the mobile market comprising portable wireless devices like smartphones and tablet PCs is growing as well, with variations in form factor increasing to meet new market demands. Driven by these applications, mobile memory unit shipments are forecast to exceed 2 billion units by 2020. These include embedded multimedia cards (eMMC), embedded multi-chip packages (eMCP), MCP and raw NAND. In concert with this growth, the embedded NAND market is undergoing a shift in protocol usage. Embedded NAND is in 80 percent of the smartphones currently on the market, and while smartphones and tablets have typically used eMMCs to store information, a transition is under way from eMMC to Universal Flash Storage (UFS) as the future of flash memory (see Figure 1).

Figure 1. UFS has taken hold, and is expected to represent half the market for NAND flash SSDs by 2020. (Source: IHS Mobile and Embedded Memory Market Tracker Q4 2016)

The JEDEC-defined UFS mobile-centric storage standard addresses next-generation mobile performance and scalability, offering fast sequential read/write speeds with high random IOPS1, which are essential for mobile phones. (For SSDs, random IOPS numbers are primarily dependent upon the storage device’s internal controller and memory interface speeds.) One key value of UFS is its ability to leverage the strengths of several existing technologies in one standard: the low power consumption of eMMC; the MIPI interface standard, M-PHY and UniPro, for the interconnect layer; and the SCSI command set as the application protocol.

Devices based on UFS 2.0, the current version of the standard, offer the highest available performance of any SSD interface standard due to its separately dedicated read/write paths, which enable UFS to read and write simultaneously. At up to 1200 Megabytes per second (MB/s), UFS operates at twice the rate of Serial ATA (SATA) 3.0 and three times that of eMMC5.0. UFS also consumes less total power by processing tasks sooner and staying in standby mode longer. Figure 2 summarizes the key benefits of UFS standard.

Figure 2. UFS offers a number of benefits that make it a superior option for embedded storage in mobile devices. (Source: Universal Flash Storage Association)

UFS is here

Adoption of UFS in the U.S. has already begun, with most of the top 10 mobile handset OEMs using UFS memory for their flagship models. While this includes primarily high-end handsets at the moment, as the cost to implement UFS continues to decline, more and more mid-tier phones will incorporate UFS-based embedded NAND memory devices. Moreover, the ecosystem for UFS is already in place, with a range of vendors supporting the UFS interface, including makers of NAND flash, systems-on-chip (SoCs), operating systems, measurement tools, and testers optimized for high-volume manufacturing (HVM).

Major NAND makers and manufacturers of UFS and BGA2 SSDs have adopted system-level test (SLT) for production use. More than 50 testers overall have been installed since the second half of 2016 for system-level testing of UFS and BGA SSDs, and this number is expected to triple during 2017.

Flexible tester optimized for embedded NAND

Memory IC makers need a class of tester that specializes in SLT of these devices, while maintaining the reliability, low cost and high volume capabilities required for conventional memory testers. Advantest developed its T5851 system-level test (SLT) solution – part of the T5800 platform series – specifically to meet these needs, delivering cost-effective testing of UFS and BGA SSDs. Built with the same proven test architecture used in Advantest’s MPT3000 family of SSD protocol test solutions, the T5851 allows customers to minimize both their capital investments and deployment risks by using the same platform and FutureSuite™ software as other members of the T5800 product line.

The flexible T5851 tester is available in both production and engineering models, allowing the system to be used for reliability and qualification testing as well as test-program development or, when equipped with an automated component handler such as Advantest’s M6242, high-volume production. As a fully integrated SLT solution, the T5851 provides multi-protocol support in one tool while its tester-per-DUT [device under test] architecture and proprietary hardware accelerator allow it to achieve industry-leading test times.

Currently, Advantest has many T5851 systems installed at IDM3 and OSAT4 customer sites worldwide for HVM production, qualification and engineering. This number is expected to increase as adoption of UFS becomes more widespread. This will be spurred by the release of UFS 3.0, as well as expansion of the standard into other applications, such as memory cards, PC clients, smart TVs, and automotive devices, which are anticipated to be the next emerging market for UFS. Advantest, as always, is working with its customers to stay on top of these developments to ensure its testers are future-ready to accommodate new requirements as they arise.

Notes:
IOPS = input/output operations per second
BGA = ball grid array
IDM = integrated device manufacturer
OSAT = outsourced semiconductor assembly and test

Interview with Ricky Sim

Q&A Interviewee
Ricky Sim, CEO & Managing Director, Advantest Singapore
By GO SEMI & Beyond staff

Singapore is home to the world’s top 3 wafer foundries, 30 major IC design centers, and offices for most of the leading fabless chipmakers and outsourced semiconductor assembly and test suppliers (OSATS). Similarly, six out of the world’s 10 largest semiconductor companies now have a presence in Malaysia. To learn more about the business environment in this region, we talked with Advantest Singapore CEO and Managing Director, Ricky Sim, who also shared his vision for the company going forward.

What do you see as the key factors driving the semiconductor industry growth in the Singapore/Malaysia region?

There is a combination of factors impacting the pace of growth here:

• The stable political environment and pro-business government policies to attract foreign investments and R&D efforts, including IP protection, definitely help. There is government support with taxes and other incentives to develop the semiconductor and electronics manufacturing ecosystem in the region.
• A ready and stable infrastructure, e.g., utilities, transportation, logistics and more.
• Access to a broad talent pool and a competitive workforce. This allows for a high degree of productivity.
• Availability of engineers, production operators, supervisors, first- and middle-level managers and senior managers – essentially, availability of talent at a reasonable cost to maintain competitiveness.
• Communication is relatively straightforward. English is the common business language, and some are also conversant in a second language, typically Mandarin or Malay. It is fairly simple for foreigners to operate in Singapore and Malaysia and, likewise, for people here to reach out to the other countries in the region.
• Both Singapore and Malaysia are strategically located in the South Asia Pacific region, with easy access to major markets and consumer insights.
• The massive growth in the Internet of Things (IoT) has helped to spur the demand for memory, wireless, microcontroller units and automotive electronics. The major players have a base in this region, and they can continue to benefit from this growth.

What needs to happen for this growth to continue?

First, global consumption must increase. The semiconductor business is very much a global business, so the major players have global presence and reach. Second, the value-add in terms of engineering content and productivity must increase. Smart integrated factories, production automation, R&D contributions and engineering value-add will be important.

Critical success factors will be the talent pool and collaborations between businesses and government agencies. The education system must attract and train young talents, and ensure that the talented individuals coming from universities and other higher education institutions have the relevant knowledge and skills to support the growth.
What impact do you believe developments in other regions, e.g., the U.K. “Brexit,” the new U.S. administration, etc., will have on the electronics business in Singapore & Malaysia?

It is still too early to tell the actual impact. This is a global business. Any uncertainties will, of course, create concerns regarding the economic outlook. Protectionist sentiments may hinder foreign direct investment (FDI) and transfer of intellectual capital. Should additional tariffs be imposed on imports, it may impact margins and/or consumption. In turn, this will place added pressure on the entire supply chain. Generally, any decisions or policies that hamper free trade and retard economic growth will impact business negatively. To mitigate the risks, governments are already working on alternative trade deals to forge forward.

How has Advantest Singapore grown in the region, and what role does it need to play going forward?

To sustain our growth in this region, we must focus on customers and their needs, and support their strategies. Knowledge transfer, productivity gain and cost optimization efforts will be instrumental. We need to anticipate trends and prepare for them in advance. We will work with customers and agencies to train and build up the talent pool while strengthening our internal processes across the regions and preparing our people to anticipate needs and to support growth.

What is your overall vision for Advantest Singapore? What growth goals for the business do you have that you can share?

Our key goals are to grow with our customers and grow multi-dimensionally. It will be essential to continually upgrade our skills, learn new technologies, build up our expertise and expand our coverage in the region.

Beyond the customer team, Advantest Singapore houses other global functions, and we look forward to leveraging the respective functional experts to support corporate initiatives and help make Advantest an even greater company!