Advantest Launches Real-Time Data Infrastructure (RTDI™) Platform Driving the Next Generation of Semiconductor Test

At the end of last year, Advantest announced that its newly launched ACS Real-Time Data Infrastructure (RTDI™) has been accepted by multiple major data analytics companies as part of an industry-wide collaboration to accelerate data analytics and artificial intelligence (AI)/machine learning (ML) decision-making within a single, integrated platform.

Advantest formed ACS in 2020 with the mission of enabling an open solution ecosystem data platform. ACS RTDI is a real-time data infrastructure that securely collects, analyzes, stores and monitors semiconductor test data to empower customers to automate the process of converting insights into actionable test decisions within milliseconds. This helps customers and partners reduce test time, optimize quality and reliability and enhance smart packaging.

“Advantest’s ACS RTDI platform turbocharges decision-making on test floor, while freeing test engineers from the tedium of having to search for needles in data haystacks,” said G. Dan Hutcheson, vice chair and senior fellow, TechInsights. “It lowers test cost with real-time test vector optimization while lowering packaging cost by shifting left systematic final test failures to probe.”

The ACS RTDI platform integrates data sources across the entire IC manufacturing supply chain while employing low-latency edge computing and analytics in a secure True Zero Trust™ environment. This innovative infrastructure minimizes the need for human intervention, streamlining overall data utilization across multiple insertions and supporting customers’ databases. Because cyber security remains a top concern among customers, the ACS RTDI platform was architected to be reliable and safe, ensuring hassle-free OS revisions, which protects data from unauthorized access or loss by leveraging True Zero Trust. Overall, the new ACS ecosystem will enable customers to boost quality, yield, and operational efficiencies, and to accelerate product development and new product introductions for years to come.

Advantest Expands Device Handler Offerings

In December, Advantest announced two new products designed to deliver advanced handling capabilities essential for the fast-growing artificial intelligence (AI) and high-performance computing (HPC) markets: the HA1200 die-level handler and the active thermal control (ATC) 2-kilowatt (kW) option for the M487x handler series. AI/HPC ICs require 2.5D/3D advanced packaging technologies to provide the high computing power necessary to generate, train and run data-intensive AI models. These ICs generate massive heat due to their high compute power, creating unique testing challenges. The new Advantest products are designed to address these challenges and help contribute to the AI/HPC market growth.

The HA1200 die-level handler for the V93000 SoC test system tests singulated and/or partially assembled die. While 2.5D/3D packages enable high computing power by enabling minimum pattern length between die, stacking die can increase the risk of mixing good and bad die, leading to yield loss. Yield loss at final test, especially for 2.5D/3D packaged ICs, can cause good die, substrates, or interposers to be discarded. Equipped with Advantest’s HPC-proven ATC technology, the HA1200 enables testing powerful, high-performance SoCs with 100% test coverage. This helps reduce yield loss at final test, thus reducing loss of final multi-die assembled product.

HA1200 Die-level Handler

The ATC 2kW solution for the M487x series (M4171, M4871ES and M4872) is designed to test AI/HPC IC packages at final test. The ATC 2kW solution features ultra-high-speed junction temperature (Tj) sensing and response technology to support high-performance ICs being tested at the set temperature and integrates Advantest’s unique force control technology to apply strong, stable, and safe contact to ICs with massive pin quantities. The ATC 2kW solution will support customers’ at-speed device test, enable safe 100% test coverage at final test while simultaneously increasing test quality and performance.

Advantest Targets NAND Flash/NVM Market with New Group of Memory Test Products

In December, Advantest announced three new additions to its suite of memory test products. The new offerings are designed to target NAND Flash and non-volatile memory (NVM) devices, which face extreme pressure to bring down test costs and cost of ownership on the test floor. The new products include the T5230 memory wafer test solution; the STM32G third-generation protocol NAND system-level test module for the T5851 memory tester; and the T5835 high-speed wafer-sort interface option.

The T5230 memory test system for NAND/NVM devices adopts a combined array architecture to achieve best-in-class cost-of-test performance for wafer test, including wafer-level burn-in (WLBI) and built-in self-test (BIST). The system can perform on-wafer test of 1,024 memory devices per test head in parallel, delivering high productivity and enabling floor space savings of up to 86%. Multiple test cells are connected per system controller in the T5230, allowing independent wafer test of each test cell. The test cells can be stored in a general multi-wafer prober while minimizing the test cell floor space, and the tester can be docked with probers in both linear and multi-stack configurations. For functional tests at a maximum test rate of 125MHz/250Mbps, the T5230 assures high timing accuracy, repeatability, and failure detection capability.

T5230 Memory Test System

The T5851-STM32G module is designed to cover the latest generation of protocol NAND devices, including UFS4.0 and PCIe Gen 5 ball grid array (BGA) packaged devices for high-speed system-level NAND testing at up to 32Gbps. Fully upgradeable and compatible with existing T5851 systems, the new module delivers tester-per-DUT (device under test) performance and is qualified for high-volume manufacturing, qualification, reliability and characterization.

T5851 Memory Test System and T5851-STM32G

Created as an option for the proven T5835 multifunction memory test system, the new high-speed wafer-sort interface enables high-speed NAND Flash/NVM wafer probing (up to 5.4Gbps) with 4,096 full I/O channels. Raw NAND die inside solid-state drives (SSDs) require increasingly higher-speed functionality, necessitating evaluation and test of die performance at the wafer level, not just in package-level final test. The solution delivers high-speed probe interface with wafer-level evaluation of memory core test functionalities during engineering production, contributing to the T5835’s overall value by delivering wider test coverage.

T5835 Memory Test System

Advantest Rolls Out Pin Scale Multilevel Serial – Next-Generation High-Speed ATE Instrument

In November, Advantest announced the Pin Scale Multilevel Serial, its newest high-speed I/O (HSIO) instrument. Designed for use with the V93000 EXA Scale ATE platform, Pin Scale Multilevel Serial is both the first native EXA Scale HSIO instrument and the first fully integrated HSIO ATE instrument to address signaling requirements for advanced communication interfaces.

HSIO interfaces, long prevalent in the computing space, have found their way into consumer interfaces such as HDMI®, DisplayPort™ and USB. In the computing space, PCI Express (PCIe) 5.0 and 6.0 are entering the multi-gigabit data-rate range and being leveraged in embedded single-board computers. Companies testing large digital designs and their interfaces, from microcontrollers and mobile application processors to high-performance computing and artificial intelligence (AI) devices, require HSIO to accommodate these high-density designs. HSIO testing is thus vital for the characterization of these new device designs as well as for early device manufacturing ramp phases. 

Pin Scale Multilevel Serial supports data rates up to 32 gigabits per second (Gbps) and is the first fully integrated ATE instrument that natively supports multilevel signaling (e.g., PAM4), which is rapidly growing in high-speed interfaces. This heightens ease of use as it enables the use of programming schemes typical in digital test, reducing test program development time and cost. As such, it helps to optimize leading-edge technologies and speed time to market by providing additional test coverage for ramping of new chip designs. 

Because Pin Scale Multilevel Serial is fully integrated, it can be easily configured into the EXA Scale platform. Competitive offerings typically require an integration stage to be mounted between the top of the test head and the interface to the device under test (DUT), degrading signal performance and worsening manufacturing integration.