EM360: A 360 View of Test Equipment Management

Managing test equipment can be a daunting task when numerous ATE systems have been installed with different configurations, at different sites, and across multiple continents. Requirements range from system maintenance tasks, such as configuration management, repair and calibrations, to production planning and asset management.

Customers of Advantest V93000 systems can take advantage of a software tool created to help them overcome these challenges and enable them to manage their V93000 installation within and across test floors. The Equipment Management 360 (EM360) tool helps improve overall equipment effectiveness (OEE), system utilization and both time to quality and time to market.

Packed with features, EM360 collects data of V93000 system configuration, and calibrations in real time for the whole test floor, and provides an overview of the test floor configuration and calibrations. Customers can check the specific details of the configuration of each system, including hardware slots and pogo pin position as well as the software version of SmarTest, and the FPGA version of the hardware. It shows the hardware change-history to help track system repair and maintenance work. The calibration management features enable monitoring and management of all calibration schedules, including system, NIST, analog and radio-frequency (RF) calibrations, as well as direct-current (DC) updates.

The Configuration Search feature can locate the targeted hardware configuration within the entire test floor while the enhanced Advanced Configuration Search can use the model file from the test program to find a system with the matching pogo position, greatly facilitating production planning. The test floor summary and board trace capabilities can help customers understand the full hardware fleet, and trace each individual board.

Key EM360 Features

• EM360-Dashboard
  • Active Tester Status List –Enhanced
  • Configurable Column
• Hardware Maintenance
  • Hardware Configuration
  • Tester Change History
  • Board Trace
  • SMT Version Management
  • Tester Comparison –NEW
• Calibration
  • Calibration Overdue Report
  • Calibration History
  • Overdue Report–NEW
  • Diagnostic Log Collector–NEW
• Tester Search (Tester Qualification)
  • Search
  • Advanced Search (by model file) –NEW
• Asset –NEW
  • Floor Summary
• System
  • Tester Setup
  • Support Time Zone Setup
  • Support Hostname Auto-change
  • User/System Configure

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Pin Scale SL: Testing High-Speed I/O Links

By Ulrich Schoettmer, Product Manager, and Frank Hensel, Application Expert, Advantest

Data rates for serial interconnect technology in CMOS are continuing to grow, driving the concurrent need for new instrumentation in automated test equipment (ATE).

Current serial technology has reached maturity – for example, PCI Express (PCIe) 2 and 3 running at 5 and 8 gigabits per second (Gbps), respectively, or SATA II running at 6Gbps – so robust standard library cells are available for various CMOS process nodes. For volume production, most manufacturers rely on DC tests, internal and external loop back tests, and therefore don’t require specialized high-speed ATE instrumentation.

However, the picture changes a bit when it comes to interface technology, which steps up to speeds of 10Gbps and higher. Particularly in the area of network processors, emerging advanced SerDes technology runs at data rates of 10, 12 and 15Gbps. These interfaces are operating in groups of eight or more lanes as “super-speed highways” in chip-to-chip or chip-to-peripheral links. Given the high levels of quality required, at-speed validation in manufacturing test is advisable to ensure that critical signal fidelity parameters are met at nominal data rates.

To meet this demand, Advantest developed a super-high-speed card for its V93000 tester platform: the Pin Scale Serial Link (SL). The Pin Scale SL instrument extends the speed and performance capabilities of prior cards in the Pin Scale family.

The Pin Scale SL is designed for SerDes, which is the serial technology used for such industry standards as PCIe, Serial ATA (SATA), Universal Serial Bus (USB) and a variety of networking interfaces. Transition to SerDes I/O links initially required significant design and validation efforts, which have proven worthwhile given SerDes’ overall benefits compared to conventional parallel I/O. These include better bandwidth, fewer I/O pads, and robustness against interference.

With a pin electronic which meets a bandwidth of 16Gbps, Pin Scale SL can serve the engineering and production needs of advanced SerDes technology. The new instrument comes with eight differential drive and receive lanes, each, on a single card.

Unique Properties of Digital High-speed I/O Interfaces

Serialized signals, instead of running off of a parallel bus, are packaged (serialized) onto a narrow path, so the serial path’s raw data rate has to be much faster to carry the same net bandwidth. Higher data rates go along with higher power, unless the signal amplitude is not minimized, but small signals are susceptible to interference and ground bounce. Therefore, serial links are usually implemented as differential lanes, which are far more immune to common mode noise. Due to the increased data rate, transmission line methodology also comes into play, so impedance control and termination become relevant.

At data rates greater than 10Gbps, frequency-dependent losses become a serious factor in printed circuit boards or cabling design. The I/O cells thus contain both active pre-emphasis structures on the drive side (finite impulse response, or FIR-based) and decision feedback equalization (DFE) on the receive (RX) side to overcome signal distortion and recover data. This makes the analog properties more complex and sensitive to process margins than in previous generations of chip design.

To simplify signal distribution, the clock reference transmission is eliminated by embedding the clock into the data stream, which leads to such encoding schemes as 8/10-bit encoding. Such coding guarantees a minimum transition density, which is the prerequisite for the clock data recovery (CDR) circuits on the receiver side to extract the clock signal from the (recovered) data stream and sample the incoming data. To ensure that the CDR circuits synchronize the sampling clock properly, it’s very important that the phase lock loop (PLL) circuit operates with minimum jitter and tracks phase variations of the incoming signal (see Figure 2). On top of the physical encoding, a transaction protocol is often utilized to organize and synchronize the data handling and ensure proper receipt of packets.

The typical list of tests needed to validate proper operation of the SerDes circuitry includes the following:

DC tests

Active equalization on the drive side is accomplished via dynamic variation in drive strength, creating a network of different current source settings that must be validated and may require trimming to work properly. Similarly, on the receive side, impedance matching resistor networks are used, which require trimming. As a result, precision DC tests are required to check output levels, swings and currents across the various settings, as well as precision leakage measurement, impedance measurements and the like.

Pin Scale SL serves these needs by providing integrated parametric measurement units (PMUs) with accuracies in the <2mV and +/- 10nA range. These PMUs are available in parallel on each I/O pin, which allows full parallel measurements, minimizing test-execution times in production.

Dynamic AC tests

 Dynamic AC tests validate the functionality of the SerDes blocks at nominal data rates. A common methodology for the TX side is to perform an eye margin test and a total jitter test. While a high-bandwidth oscilloscope is suited for performing such tests in the bench environment for engineering purposes, a more streamlined multi-point eye mask test can be performed in the ATE environment, as shown in Figure 3. In the ATE environment, the measurement follows a bit error rate (BER) of a pattern stream-based approach, which allows for test coverage on both the TX and RX sides. For this task, the device under test (DUT) is turned into a test mode to generate a pseudo random binary sequence (PRBS) at full data rate, while the ATE receiver is used to scan the data stream along the voltage and timing, or phase, axis.

High-resolution verniers (i.e., movable graduated scales) for comparator threshold and sampling timing allow collection of detailed shmoo plots (much like a sampling scope plot) or may be used to scan to “open eye area” for eye width and height against a predefined multi-point mask. For very fast collection of total jitter budget measurement, a time measurement unit available on the Pin Scale SL card per pin/lane comes in very handy.

On the RX side, it becomes important to stress the signal recovery properties of the circuitry. For that matter, the ATE instrument sends PRBS signals to the DUT with high fidelity, an example is shown in Figure 4. By adding additional distortion (highly attenuated signals) and/or with superimposed jitter. Signal properties like drive amplitudes, signal equalization and jitter-injection generators are the programmable tools that come to play in order to emulate real-world, worst-case DUT conditions.

 Additional Measurements

Frequency offset tests are relevant to validate that the “remote” end of the communication path properly synchronizes to the data stream, especially in the networking application space. As a result, emulating a certain frequency (phase) offset between the TX and RX data streams to make sure the CDR still syncs properly is a mandatory test process. Programmable frequency verniers, down to the parts per million (ppm) offset versus nominal settings, are very helpful. Test vehicles for these tests are also PRBS signatures. Pin Scale SL supports the above tests via programmable PRBS generator and analyzer hardware blocks, which, again, are available on a per pin/lane basis.

Generic ATE tests

Besides their high-speed specific properties, these pins often also serve as the structural access path for all sorts of logic scan tests. For that purpose, the high-speed instrument also has to support “classic” pre-stored vector generation and truth table compare. Pin Scale SL also supports this use model and features a full-blown digital vector generation and compare engine behind every single node, which is fully compatible with Advantest’s mainstream digital pin card offering (Pin Scale 1600).

Protocol emulation support in HW

Pin Scale SL features a standards-compliant PCIe protocol stack, which allows high-level communication to the DUT. Other protocols, e.g. SATA, are also under development.

Looking Ahead

The Pin Scale SL Instrument provides enough headroom to be ready for the next generation of ASIC designs, which will be running 15Gbps links. PCI Express Gen 4, which is also under development, will be running 16Gbps and is anticipated to start emerging in 2015/2016. Besides standards, a number of proprietary SerDes links are under development that fall into the sweet spot of Pin Scale SL availability.

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T2000 IPS Solution for Power Device Testing

By Amit Monga, Business Development Manager, ASD Product Group, Advantest

Introduction

Integrated circuit devices that fall under the general power device category are getting more mainstream. The devices form an important part of a number of very fast growing industries including but not limited to the wireless, automotive and industrial industries. On the wireless side, PMIC devices are having significant growth as the need for battery management and LED driver integrated circuits grow. The automotive market sees a larger appetite for electrical components with safety (example: ABS, Power steering) and luxury (Example: infotainment systems) primarily driving this area of growth.

Source: Power Management Market Tracker – Q4 2013

Challenges and Complexity of Power Device Testing

As power device uses increase, so does the need to test them adequately. The wireless market, driven by smartphone and tablets requires device testing to be done at the lowest cost possible and yet the ever increasing integration of functionality in the devices means the IC has a lot more functionality. The average selling prices for the devices are very low and test budgets are limited. The test solution has to address this as well as ensure test quality is not compromised.

The increasing integration poses a second challenge. The test demands are increasing. A few years back, power devices could be tested on a purely analog tester with a few power supplies. Now, a basic device requires some digital stimulation, high current and voltage requirements, and some are even integrating RF IP. Internet of Things (IoT) type devices are a perfect example of this increasing integration and complexity. Tester selection is therefore not based on a single device type but seen from a solution stand point. The selected platform should be scalable to accommodate the rapidly changing devices.

A general trend that is not particularly related to power devices but more to do with the shrinking process nodes is the decreasing supply voltages. This is especially true for wireless and consumer devices. PMIC devices such as the fuel gauge found in a number of smartphones are an example of devices that are required to monitor these voltage levels. This requires the chips to have very accurate voltage reading capability as well the ability to provide very precise biases. The capability is down to the sub 100uV range and test fixtures are having to redesign their modules to meet this challenge.

 

DC Challenges:
Lower voltages,
More supplies,
Tiny power specs

 

The other challenges facing power device test are common across other family of devices. These range from minimizing test times, reducing time to market, maximizing parallelism and number of devices that can be tested at the same time and ensuring that the load board does not limit the parallelism. This is especially true for automotive power devices because each device requires a large number of on board components. The load boards that for other types of devices can test up to 64 or even 128 devices in one go suddenly seem inadequate for even 16 site testing of automotive parts. The major reason being the real estate available on the boards. Tester companies are aware of this and are continuously coming up with better module and load board design to counteract this.

The T2000 IPS Solution

The T2000 test platform is a scalable platform with modules that provide solutions for different device types and industries. The IPS solution refers to a particular set of modules that when populated into the T2000 tester, form a solution for power device testing. The modules provide a broad coverage and cover a whole range of different IC types.

The T2000 IPS modules are designed to target some of the key challenges that power devices face during test.

The modules have special multifunctional architecture (PMU, TMU, DGT, and AWG in one pin). This ensures that each module has a wide capability. This specially targets the increased complexity of devices, and ensures a large number of different tests can be handled by limited number of modules. The overall impact of this for power devices is not only a lower test system cost, but also having so much functionality per pin implies less load board space is wasted on relays. An Example of this would be a pin that for one test requires a PMU resource but for the next test requires a TMU resource. In addition, the MPCM module, a relay module that routes signals internally in the test head also leads to a reduction of load board relays. Overall in some cases this unique architecture has led to almost 40% reduction in the components on board as compared to conventional architectures.

The specifications on the MMXH PMU are also targeted towards PMIC and other devices that require high precision voltage source and measure. The solution has been successfully used with high precision Li-ion battery monitoring circuitry as well as band gap reference IC where stability and accuracy are key. In addition the modules provide high stability current measurement capability.

Some example test connections are shown below:

 

 

 

 

 

 

 

 

 

 

 

The other key advantage that the T2000 provides is the multisession architecture. This basically allows the tester to be accessed by more than one user and for more than one user to simultaneously debug tests online. This reduces the overall engineering development time and leads to much shorter time to market. The test modules are specially designed to take advantage of this architecture.

Representation of multisession architecture

Summary

Testing of power devices for test solution providers has to be looked at from both a business and a technological point of view. Factors like time to market, cost of test, test time are key to making a business decision on the type of test platform but hand in hand, factors like device trends, accuracy, test coverage and stability weigh in. The T2000 IPS provides a comprehensive solution that targets both these selection criteria.

About the Author:

Amit Monga has a bachelor’s degree in Electrical Engineering from McGill University and an MBA from University of Toronto. He joined Advantest in 2006 as an application engineer and has experience in digital and analog SoC device testing. He is now part of the Business Development team at Advantest and focuses on developing strategies to address the power and image sensor test market.

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W2BI Unveils SmartBox – an Innovative System Level Test Solution for Smart Device Testing

By Artun Kutchuk, Vice President, Business Development & Strategy, and Keith Schaub, Vice President, Corporate Development, W2BI, Inc., Advantest Group Company

Combining W2BI’s patented QuikStress^TM Automated Smart Device Test Software with 3D Robotics

Smartphones and other smart devices are continuously integrating new functions. Many of these functions are physical movements (i.e. NFC, vibration, gyro, compass, accelerometer, temperature, and health / fitness to name a few). However, most test solutions today still target the non-physical aspects — the software, applications, RF and other specifications. As a backdrop to facilitate our discussion, let’s focus on three key life cycle segments of the smartphone:

• Pre-Launch production testing
• Post-Launch / Reverse production testing
• Point-of-Sale / In store diagnostics and testing

Each of these life cycles are closely related in the types of testing and diagnostics performed. To highlight that, let’s talk about some problems Alex, Tim, and Vicky are having with their smart devices.

Alex recently purchased a new smartphone but is having some audio issues when listening to music on his headphones. Tim has had his smartphone for about 6 months and recently his touchscreen hasn’t been working properly. Sometimes his phone doesn’t register when he swipes or presses the screen. Lastly, Vicky has been missing important phone calls and finally discovered when in silent mode, the phone isn’t vibrating like it is supposed to.

I’m sure many of you have experienced similar problems. Typically, the first thing you would do is to take your phone back to the Point-of-Sale (store where you purchased it) and inform the store assistant of the problem. Now what? Well, the assistant asks if you can show him the problem. Sometimes you can, when it’s a hard failure, but often you can’t. It might be intermittent, or occur only after certain events, or it might be caused by a specific combination of interactions between the hardware, software, applications, etc. Some stores have software diagnostic tools that perform a gross health check, but often the problem or issue is scenario based, therefore the diagnostic tool typically won’t capture or flag the failure, so the phone gets marked as NFF (No Fault Found), or NTF (No Trouble Found). Conservatively, we’ve estimated that NFF/NTF classifications are costing the industry in the 100s of millions of US dollars, perhaps in the billions.

There are two main reasons for that. First, in the store, the assistant typically will swap out your phone, giving you a new phone, so already a few hundred dollars to give the customer a brand new phone. Second, the NTF phone then churns through the reverse production line where numerous tests are run at multiple test stations looking for the problem, when no fault is found, the phone gets wiped and resold as a refurbished unit. Someone has to pay for all that testing and refurbishing. There are entire 2^nd and 3^rd tier markets existing largely based upon the high quantity of NTF/NFF phones. So, it would be safe to say that it is a big problem when the problem itself subsidizes entire markets.

There is a rule of thumb in industry for an end-user:

• In the first occurrence of the problem –> Change the phone
• In the second occurrence of the problem –> Change the Operator

The first time a customer has a problem with his phone, the customer is annoyed, would most probably change the phone – get a new one or upgrade to a newer model. If the store had to send his phone to the repair center, then he is without his phone for several days.

Then second time he has a problem, now he is extremely frustrated. The operator didn’t fix it the first time, and now he has to go through this again, so there’s a very good chance that he will switch operators.

You might ask. Didn’t any of this get tested at pre-launch? In fact, yes, smart devices with their myriad of integrated functions including: audio, touch screen, video, FM, BT, WiFi, NFC, compass, gyro, accelerometer, etc.), literally require a small army of people manually testing each function. The testing is highly subjective and prone with human errors and each function is generally tested standalone – that is, non-scenario based. Additionally, the emerging Internet of Things (IoT) devices are further complicating testing with high mix and low volume complex test setups.

This has created a need for a new platform that is low cost, easy to use, and automated consisting of robotics, and system level software able to interact and test functions, user scenarios, mission modes, and applications.

At W2BI, we developed an innovative platform, SmartBox, that:

• Functionally tests key components of a smart device at pre-Launch Production, Point of Sale (POS) and Repair Depots completely automated with typical end-user scenarios
• Scales the features and functions appropriately for the three key market segments (i.e. Pre-Launch, Point Of Sale, Post-Launch)

The Key Values & Benefits to customers

• Reduce NTF/NFF
• Isolate quality issues
• Classify true failures
• Eliminate subjectivity
• Verify & validate repairs
• Increase Customer Satisfaction

W2BI’s SmartBox platform combines robotics with system level software designed to be a low-cost scalable profile with a simple and easy to use experience for Production Testing, Point of Sale and Return Depot end users. All major functions as well as integrated applications and user scenarios can be tested automatically.

In addition to testing the software, OS, UI, applications, and user scenarios, SmartBox will be able to test the physical functions, namely:

• Touchscreen
• Audio / Video
• Camera / Lights
• Vibration
• Accelerometer
• Physical Buttons
• Compass
• NFC / Wireless Charging
• Gyro
• Temperature
• Health & Fitness

With SmartBox:

• Point of Sale: A store assistant can potentially place the smartphone inside, chose one or more tests including scenarios and within a few minutes get back a non-subjective actionable assessment.
• Pass/Fail result. Reverse Logistics / Repair Centers: Quickly and easily verify a failure as well as verify a successful repair and eliminate subjective errors caused by manual testing.
• Pre-Launch Production: Automatically test and verify all of the physical functions eliminating manual labor and human error.

About the Authors:

Artun Kutchuk has over 25 years of experience in wireless, aerospace, robotics, business process automation and software development. He holds an M.Eng. Degree from McGill University. Artun also has co-founded a start-up and holds several patents in mobile device testing and diagnostics. Prior to W2BI-Advantest, Artun held multiple positions at Carrier IQ, Ericsson, Interfacing Technologies and CAE.

 Keith Schaub has worked in RF & Wireless Semiconductors for more than 20 years. Keith is the author of Production Testing of RF and System-On-a-Chip Devices for Wireless Communications. He holds five patents on various wireless devices and test systems, founded two start-ups, and is an avid writer and publisher on wireless topics.

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