Enabling High-Volume Optical and Electrical Test on 100Gbps Optical Interconnect Devices

By Tasuku Fujibe, Consulting Manager, and Hiroyuki Mineo, Senior Engineer, Advantest

High-speed data communications demand is rising at astronomical rates. According to a forecast from Cisco Systems, the volume of global data center traffic is expected to increase to more than 10 zettabytes per year in 2019. In response, new network architectures are being considered, while data centers are being housed in much larger buildings. As this requires interconnection devices (switches, routers, etc.) to support distances of as much as several kilometers, using electrical interconnection devices in these very large data centers is becoming impractical. Moving forward, optical interconnection devices will need to be implemented in high volumes, creating new test challenges. Currently, rack-and-stack solutions are used to test these devices, but new manufacturing approaches are needed to avoid the bottlenecks such approaches can create.

To answer this demand, Advantest has developed a test solution with the ability to cover high-speed interconnection devices, both electrical and optical – particularly those destined for high-speed datacom applications. Designed for high-volume manufacturing, the T2000 scalable test platform can be configured to test current digital signal processors (DSPs) as well as high-speed buses and communication interfaces due to its modular architecture.

Platform offers high flexibility

The T2000 ATE solution consists of a high-speed optical/electrical test module, a low-speed digital module for I2C ports, and a device power supply module (Figure 1), all of which are integrated into the test platform. The test module’s 64 ports can operate up to 28 Gigabits per second (Gbps). This includes 32 optical ports – 16 transmit (TX) and 16 receive (RX) – and 32 differential electrical ports (16 TX and 16 RX). The T2000 platform also includes high-performance device fixture technology for both the optical and electrical ports to perform device interface.

To understand the benefits the T2000 platform enables, let’s take a closer look at the device fixture and the high speed optical/electrical test module.

Device fixture and test module

The device fixture provides both optical and electrical signal connections between the device-under-test (DUT) and the test module. To test optical lanes, the device fixture must support such optical assemblies as MT-connectors. However, ordinary MT-connectors have a limited insertion lifetime (typically, less than 300 insertions), making them inappropriate for this application. To overcome this limitation, Advantest has developed a high-volume-capable non-contacting optical connector that is fully compatible with MT-connectors.

Figure 2 shows the new optical connector and illustrates the approach used for its fabrication. Using a gradient-index (GRIN) lens to maintain a working distance of 150 microns (µm) enabled development of a high-performance optical connection with no physical contact between the end of the fiber-optic cable and the connector.  Because the new connector is MT-connector-compatible, it can be used to make contact with MPO connectors, which are typically used in compact QSFP+ PSM4 transceivers used for data communications.

The high-speed optical port block diagram is shown in Figure 3. FUNC ASIC has pattern generator (PG) and bit error rate tester (BERT) functionalities, both of which can operate up to 28 Gbps. For electrical ports, the FUNC ASIC is connected to the DUT via the device fixture. For optical ports, the output test signal from FUNC ASIC goes to the optical modulator to modulate the continuous wave laser provided by the laser source. Variable optical attenuators (VOAs) adjust output power to the DUT to test the DUT’s receiver sensitivity. The optical signal provided to the DUT is connected to a photo detector and trans-impedance amplifier (TIA) in the test module to convert it to an electrical 28-Gbps signal. Then FUNC ASIC captures the signal to measure eye diagram by using its BERT capability.

Measurement results

During device fixture evaluation, insertion loss variation was measured against iterations. The results, seen in Figure 4, showed stable insertion loss variation of less than +/-0.3 dB during 100,000 repeated operations. Compared to ordinary MT-connectors, which have an anticipated lifetime of less than 300 cycles, this connector can provide stable measurement with a longer lifecycle.

Current 100-Gbps datacom transceiver interfaces, such as PSM4, CLR4 or CWDM4, use four lanes of both optical and electrical 25-Gbps lanes to achieve aggregated band width of 100-Gbps. The test module has 16 lanes of both optical and electrical high speed ports. The scalable platform can simultaneously test four DUTs per optical port module; integrating two modules onto a test solution thus allows parallel test of up to eight DUTs. Multi-site testing increases system throughput and significantly drops per-site equipment costs.

Summary

The semiconductor industry roadmap for optical transceivers – advanced semiconductor devices that transmit and receive data through optical fibers – calls for boosting speeds from today’s 40-Gbps interconnections to as much as 400-Gbps by 2020. Advantest’s T2000 solution is among the first integrated solutions able to cost-efficiently test these high-speed devices.

Since typical 100G transceivers use four 25-Gbps ports to achieve aggregated bandwidth of 100-Gbps, the T2000 configuration allows four 100-Gbps devices to be tested simultaneously, improving test throughput and reducing system cost. It also includes a device fixture solution that provides stable and longer-lifecycle non-contacting optical connectors, making the system well suited for high-volume manufacturing environments.

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IoT Devices Require a New DFT Paradigm and Scalable ATE

By Neils Poulsen, Director of SoC Business Development, Advantest

Touted as the “next big thing” to drive the next major wave of semiconductor device growth, the emerging market for the Internet of Things (IoT) is widely projected to increase semiconductor device volumes by tens of billions of units over the next several years. These volumes will be fueled by myriad new consumer end-user applications and services, to be provided by hundreds of companies ranging widely in size and resources.

IoT devices comprise several functions: computation (typically a microcontroller); communication (typically a wireless/radio frequency [RF] connection); and multiple sensors and/or actuators, the quantity of which depends on the end-use application. Sensors are used to detect environmental parameters, such as temperature, acceleration, magnetic field, moisture, light intensity or distance. The received signals are processed via integrated microcontroller or DSP cores, and the information is passed on to wireless devices via wireless communication interfaces. The integrated cores’ performance is significant, as data encryption is often required due to security aspects in IoT products. Other key functional components in smart devices are drivers for actuators to convert electrical signals into movements. Typically, these are integrated driver circuits for brushless DC motors or relay drivers.

Because these devices must operate on small batteries for extended periods of time – sometimes years – they must be able to consume very low amounts of power. Bluetooth Low Energy, ZigBee, WiFi and other communications standards are designed for low power requirements and optimized for easy network integration. This combination of requirements presents many challenges to designers and test engineers, as these complex devices are increasingly becoming more like high-end systems-on-chip (SoCs), but necessarily sell at a small fraction of the price.   

Moreover, the dynamic nature of the consumer market, as well as the large number of competing companies, is placing tremendous pressure on semiconductor suppliers to shorten both their time to market (TTM) and time to quality (TTQ). Improving these parameters will allow them to secure customer design wins and achieve the necessary volumes and quality levels their customers require – at the same time, meeting their own cost targets, including acceptable manufacturing yields (see Figure 1).

Figure 1

To profitably compete in the IoT market, companies must find ways to significantly increase their overall efficiency and reduce their overall costs. This means they must consider breaking away from their traditional approaches and embrace a new paradigm for the design-to-manufacturing process, including test.

Changing the paradigm

In the traditional process flow (Figure 2), design and DFT (design-for-test) engineers use test instrumentation in benchtop setups during initial device bring-up to debug and verify the chip’s proper operation. This includes building special fixturing to interface the device-under-test (DUT) to various multiple instruments, as well as translating patterns from the design simulation environment into test vectors that can execute in the benchtop instruments to control and stimulate the DUT. To test complex IoT chips’ complete functionality (i.e., digital, analog and RF) as they become more integrated, these engineers typically write time-consuming custom software routines to control and coordinate multiple benchtop instruments.

Figure 2

Similarly, in the next step of the traditional process, the characterization phase, engineers typically use benchtop instrumentation to evaluate the chip’s performance, validate specifications, and determine operating margins across a range of operating conditions, including frequency, voltage and current. This can be a time-consuming, manual process. In addition, the instrumentation, device fixturing and custom software routines usually differ from those used in the design verification phase. This leads to inefficient duplication of engineering resources and can create delays in the overall process.

To garner a statistically valid sample, many devices should be characterized, but collecting and analyzing the large amount of data needed to do this is limited by the slow throughput and difficulty of interfacing bench setups to automated device handlers. As a result, because of TTM pressures, only a few devices usually receive this high level of characterization, and the range of operating conditions is limited, which can negatively impact quality and device yields later during the manufacturing process. This is also typically the phase when customer samples are first provided, based on characterization data, so time-consuming benchtop characterization limits the number of sample devices that can be shipped to customers, which can limit market potential.    

In the next phase of the traditional process, test engineers develop test programs on ATE that will be used to test the devices in high-volume manufacturing (HVM). However, the ATE instrumentation, DUT fixturing and software environment are all very different than the bench set-ups. This means there is very little compatibility between the earlier Design Verification and Characterization phases and the HVM Test Program Development phase. Once again, this results in duplication of engineering effort, including designing new DUT interface fixturing, performing additional ATE characterization to correlate to the benchtop characterization data, and determining test limit guard-bands to ensure HVM test quality. The different environments also mean that correlating the HVM test results to the benchtop data can be difficult and time consuming, requiring multiple iterations and further delaying TTQ.

Implementing a new approach

A new integrated ATE solution being embraced by several leading semiconductor suppliers utilizes engineering ATE that comprises the same hardware instrumentation, software environment and DUT interface fixturing as the ATE used for HVM test (Figure 3).  This compatibility accelerates test program development and bring-up, correlation and release to HVM by leveraging the engineering efforts from the previous phases – resulting in reduced costs and improved TTQ.

Figure 3

Design/DFT engineers can utilize low-cost engineering ATE for their initial device debug and verification so that when they translate their simulation patterns to test vectors, these same vectors can be used by test engineers for their HVM test program. This eliminates redundant vector translation, enables test engineers to begin test program development earlier, and minimizes problems and delays due to revision errors.

Similarly, by combining low-cost ATE with a cost-effective engineering handler, an automated “production-like” environment and high-throughput characterization test programs, engineers can realistically characterize thousands of engineering samples in far less time, significantly reducing TTM. And by collecting and analyzing much more data over a far wider spectrum of operating conditions, they can significantly increase quality.

Advantest V93000 platform handles multiple requirements

Advantest is enabling this integrated test approach via its V93000 platform of testers, which includes the scalable A-Class configuration. A cost-effective engineering ATE solution, the A-Class uses the same hardware instrumentation, software and DUT interface fixturing as the other members of the V93000 family (see Figure 4), facilitating transition across the V93000 platform as needed. This includes high-density instruments that utilize the universal pin concept (every pin can generate and receive the digital, analog or RF signals needed to test IoT devices).

Figure 4

Utilizing the V93000 A-Class in engineering for design verification and characterization creates a seamless streamlined process, in which:

• Performing the initial device debug and bring-up on the same DUT fixturing that will be used in HVM enables removing the loadboard from the critical path;
• Reusing common test routines speeds up the entire DV-to-HVM process and can result in having the HVM test program complete with first customer samples; and
• Automated high throughput characterization (in conjunction with an engineering handler) provides faster and higher-volume data collection, on a significantly larger number of devices.

Implementing the Wave Scale RF channel card makes the V93000 A-Class even more effective as an economical engineering option for the IoT market. Wave Scale RF was designed with four independent subsystems per board to eliminate shared pin resources. This enables both in-site and high multi-site parallel testing, helping achieve test time reductions of up to 50 percent or more, compared to traditional RF architectures.

Through the combination of all these capabilities that allow users to conduct their engineering activities on the same platform and instrumentation set that they use for high-volume production, Advantest has developed a scalable solution that improves engineering efficiency, lowers overall costs, reduces TTM and improves TTQ – helping semiconductor suppliers to compete in the emerging IoT market.

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Known-Good-Die Testing of Complex Digital ICs

By Dave Armstrong, Director of Business Development, Advantest America, Inc.

Large, thin and high-power digital ICs pose a number of challenges to the test process necessary for achieving true known-good-die (KGD). As these costly, fragile devices are destined for advanced 2.5D and 3D packaging solutions, advanced test capabilities and solutions must be implemented to reduce scrap assemblies and improve product margins.  Producing a true KGD prior to assembly requires bringing final test and potentially system-level test content forward, executing it at the die level.  This calls for an advanced thermal control (ATC) system, similar to what is traditionally used at final test, as well as fine-pitch probe alignment capability that exceeds the capability of leading-edge wafer probers.  These are the two areas that Advantest aims to address with its die-level handler. To understand the product’s benefits, it’s important to look at the packaging landscape that gave rise to its development.

The assembly and packaging process is changing rapidly, with multi-chip assemblies becoming mainstream.  When multiple devices are assembled together in one assembly (either 2.5D or 3D), the yield risk is driven by the lowest yielding device. Unfortunately, costly, high-yielding memory stacks may need to be scrapped because of undetected faults on other devices in the assembly.

Further complicating this situation is that high- and/or low-temperature testing is often needed to detect many of the marginal faults in a device.   Traditional wafer probers lack a thermal control system responsive to on-die temperature variations.    Other techniques (sticky tape, wafer frames, etc.) lack a viable thermal interface to the device-under-test (DUT), making thermal control very difficult or more likely impossible.

The Advantest HA1000 die-level test system reduces the risks associated with 2.5D and 3D assembly, providing a way to handle, chuck, probe, and thermally control singulated thin die, die stacks, 2.5D assemblies, and even partially assembled 2.5D devices. Features support probing of pads, bumps, pillars, or even through-silicon vias (TSVs) with pitches down to 50 microns or smaller.

Today’s KGD test challenges

The earlier KGD tests can be performed, the lower the test and yield costs, as well as the overall cost of goods sold. Today, both memory and logic performance testing and burn-in are being implemented as early as possible in the device test flow. This KGD testing of multi-die, 2.5 and 3D devices at the die level prevents more costly yield loss later at package-level test, as it identifies process problems earlier so they can be corrected to prevent assembling bad die on otherwise good assemblies. Without this step, yield cost will be higher in 3D chip manufacturing and 2.5D and 3D packaging, as well as for systems-in-package (SIPs) and multi-die devices.

Package-level testing usually runs high-performance tests prior to board and system assembly, driving up power and thermal control requirements. Additionally, package-level burn-in can increase this requirement by 1.5x to 2.5x and drives ATC requirements. As chips and systems become more integrated using 3D packaging technologies, this performance and reliability KGD testing will be required much earlier, at the wafer and die levels, before package assembly.

Pre-assembly die-level and partial-stack test insertion could provide a way to execute high-power thermal tests. The Advantest HA1000’s ATC, together with an extremely low thermal resistance, supports high-power scan tests, elevated voltage screens, dynamic voltage screens and other test techniques to perform die-level sorting prior to stacking. This increases the shipped products’ quality level and screens for new reliability defects that may have been introduced during the thinning, bumping and sawing steps.  Due to the reduced thermal mass, the ATC can also perform single-pass, multi-temperature testing by cycling temperatures several orders of magnitude faster than traditional wafer probe systems.

The value of adding a test step

While it is possible to use this type of prober to replace wafer probe itself, it’s proving more valuable when additional test insertions are made into a traditional manufacturing flow. Adding a pre- or partial-assembly test step requires a financial analysis to confirm its return on investment (ROI). Figure 1 indicates that the return on the test investment is 10 percent or more if the product yield is less than or equal to 93.3 percent (assuming the COT is a conservative 10 percent).

Figure 1: Single Chip = Value of Testing (ROI)

When considering the addition of a new test insertion prior to an assembly step involving the cost of additional chips, the same approach can be utilized to determine ROI.   As shown in Figure 2, if the additional chips (or interposer/package) are 3x the cost of the component being added, the ROI for additional testing prior to assembly is 10 percent or greater if the yield of the last device is less than or equal to 99.6 percent.   Of course, a more realistic back-end yield would provide a significantly higher ROI. 

Figure 2: Single Chip = Value of Testing (ROI)

A new approach: singulated die handling and testing

The Advantest HA1000 is a device-level handler for bare die stacks and partially assembled devices. Main features include precise, vision-based alignment; the ability to handle a wide range of device sizes and thicknesses; support for very high-pin-count probing; and integrated high-power-capable active thermal control.  Depending on the size of the device and temperature setpoint, the HA1000 can heat or cool parts of up to 300 watts. The handler incorporates a flexible, dual-fluid thermal control system that can accommodate temperatures in the range of -40°C to +125°C.

A prime advantage of the die-level tester is that it allows devices to be tested after wafer thinning, bumping and dicing. Testing devices in die form detects not only faults from the assembly process (chipping and cracking) but also untested faults, which are typically handled at final test, for more complete KGD test.

Placing and probing thin die

Probably the most critical step for probing raw thinned devices is a world-class vision alignment system capable of positioning the probes appropriately on top of the fine-pitched device structures. For large and high-power thin die, an additional challenge is to apply enough probe force to ensure equal low contact resistance and thermal resistance across the entire die while not damaging the thin die.

The chuck must be carefully balanced to provide good surface area for thermal conduction. The HA1000 does this by using a monitored three-zone vacuum, ensuring that all corners of the die make solid thermal contact to the chuck. If suitable vacuum is not achieved in all three regions, an alarm sounds and the test stops.  The chuck is carefully designed, using micro-channel technology, to avoid hot spots or temperature gradients.   

Conclusion

The Advantest HA1000 provides the industry with a unique opportunity to achieve true known-good devices at the die level – prior to assembly. By carefully positioning thin or thick, large or small devices on a fast-responding thermal chuck, it enables final and/or system-level testing to be conducted earlier in the manufacturing sequence. Performing this extended testing prior to assembly helps ensure that all the parts integrated into a 2.5D or 3D structure are high-yielding, highly reliable devices.  Further, this additional test step reduces scrap assemblies and reduces product cost.  As a result, the ROI for an additional die-level test step is excellent.

For further reading:

Known-Good-Die Test Methods for Large, Thin, High-Power Digital Devices by Dave Armstrong and Gary Maier; International Test Conference, 2016.

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