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Advantest to Exhibit Wide Range of Semiconductor Test Solutions Enabling 5G Connectivity at SEMICON Japan on December 12-14

 

Advantest Corporation will feature more than a dozen of its advanced test solutions that enable 5G connectivity for such diverse applications as mobile electronics, medical devices, automotive systems, retail business and big data at SEMICON Japan 2018 on December 12-14 at Tokyo Big Sight.

“This year, we are showcasing our range of capabilities in measuring the connected world and everything driven by 5G communications,” said Judy Davies, Advantest’s vice president of global marketing communications.  “The product portfolio that we have – and are continuing to develop – is designed to meet the global market’s requirements for 5G in applications from next-gen smart phones to connected cars.”

Product Displays

Among the products that Advantest will feature in booth #2044 in Hall 2 are eight new systems and enhancements that the company has announced within the past year.  These include three new members of the B6700 product family of burn-in memory testers – models B6700D -S and -L – designed to boost parallel testing capacity and lower the cost of test for NAND flash devices; the newest additions to the MPT3000 platform that make it the industry’s first fully integrated test solution for developing, debugging and mass producing PCIe Gen 4 solid-state drives (SSD); the FVI16 floating power VI source that extends the V93000 platform’s capabilities to include testing of advanced ICs for automotive, industrial and PMIC applications; the new T5503HS2 system, the only tester of its kind to evaluate the advanced features of next-generation, high-speed LPDDR5 and DDR5 memory ICs; and two new modules – the multifunction mixed high voltage (MMXHE) and multifunction floating high power (MFHPE) units – that enable systems in the established T2000 series to more efficiently test devices used in the power trains of electric vehicles.

The booth will include an automotive display to help show attendees visualize how and where Advantest’s equipment is being applied to improve the performance and reliability of on-board electronics, from LIDAR systems to mobile communications.

Other products on display will be the flexible T5851 memory tester for next-generation mobile protocol NAND such as UFS3.x and PCIe Gen4 BGA; the T6391 system for testing LCD drivers; the EVA100 measurement system, which has a new HVI (high-voltage VI source and measurement) module that extends the platform’s range to include high-power ICs used in large-volume consumer applications; the portable, remotely operable M4171 handler, capable of automated device loading and unloading as well as active thermal control (ATC); the E3650, a new high-end model of MVM-SEM enabling next-generation photomasks; the F7000 e-beam lithography tool for the 1X-nm technology node; and probe cards optimized for use in Advantest’s testers.

Company experts will be on site to answer attendees’ questions about the latest test technologies and best practices.

Sponsorships

In addition to exhibiting, Advantest is a gold sponsor of this year’s SEMICON Japan.  This includes sponsorship of the Presidents Reception networking event on the evening of December 12 and the SEMI Technology Symposium (STS) on “Challenges to Test Diversity” to be held at TechStage South on December 14.

Advantest also is the sole sponsor of the inaugural SMART Transportation Summit in reception hall A in the Conference Tower on December 13.  Judy Davies, Advantest’s vice president of global marketing communications, will present the inaugural address for the Summit, at which automotive manufacturers will discuss technology advances and business prospects associated with smart and electrified vehicles.

The four-hour event will open with a session in which automotive industry executives from Toyota’s Info Technology Center, Volkswagen and Honda’s R&D organization will share their perspectives on the future of automated driving, electrified vehicles and connected cars.  Following a luncheon, the program’s second session will feature semiconductor industry representatives from Denso, Bosch and Infineon discussing innovations in transportation systems and what the future may hold for both business and technology.

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Posted in Uncategorized

Q&A Interview with Ira Leventhal

By GO SEMI & Beyond staff

This issue, we delve into a subject of growing interest in the test world and beyond: artificial intelligence. Our Q&A interviewee is Ira Leventhal, Vice President of Advantest America’s New Concept Product Initiative, a position he has held since June 2017. Ira has over 25 years of ATE industry experience, with Hewlett-Packard, Agilent Technologies, Verigy, and Advantest.

Q. Why is now the time for AI to be implemented in the semiconductor industry, given that it’s been discussed for many years?

A. Since Alan Turing first postulated in 1950 that the computer equivalent to a child’s brain could be developed and then trained to learn – evolving into an adult-like brain – we’ve been waiting for the technology to catch up to his theory. Today, all the key components essential to enabling AI are in place. First, you need a lot of data, and the Internet of Things facilitates this. Second, you need access to the data; using cloud computing and Big Data technologies, data silos become data lakes with easy access. Third, you need to fast data crunching, which we can achieve thanks to the tremendous advances in computational power and parallel processing. And finally, you need better algorithms for a wide variety of applications – the first three items have enabled rapid advancements in algorithm design.

Q. You state that advancements in deep learning will fuel the next semiconductor industry revolution. How so?

A. For years, the test industry has used adaptive test and other techniques to streamline and focus test efforts for maximum value (and minimum test times). With the advent of AI technologies such as neural networks, new possibilities are coming to light. Merging these approaches will allow the industry to improve device quality, reduce cost of test, and automate the control of functions best suited to the computers supporting us – freeing humans to concentrate on new developments and innovations.

Q. What is deep learning? Is it synonymous with AI?

A. Many people don’t realize that AI, machine learning and deep learning are not interchangeable terms. AI is actually an umbrella term, and the others are nested subsets of AI. [See Figure 1].

Figure 1. AI vs. machine learning vs. deep learning

Q. Why should we focus on deep learning?

A. Deep learning is analogous to building a skyscraper. When you don’t have sufficient land to build a very large building, you go vertical. When you lack infinite storage, computing power and training data needed to build a very large single-layer neural network – which we do – you go deep. Deep learning promotes efficient use of available resources, much like a skyscraper, and it enables complex problems to be broken up into a series of steps, similar to an automobile assembly line.

Convolutional neural networks (CNNs) are used heavily in deep learning network architectures. When the network is being fed images during the training process, convolutional filtering layers are used that can recognize specific attributes of the images. As each layer views an image through a convolutional filter, it passes on a reduced set of data to the next layer, enabling the network complexity to be kept in control as you go from one layer to the next. The reduction in complexity of a CNN vs. fully connected networks minimizes processing, memory, and time required for image recognition. [See Figure 2.]

Figure 2. How a convolutional neural network works

Q. How can deep learning be applied in semiconductor testing?

A. A type of deep learning called transfer learning is well suited to our industry. Transfer learning enables you to start with an existing set of trained data instead of having to train a network from scratch. If you take a network that was trained with millions of images and you keep the initial layers that can understand low-level aspects of the images, you can replace later layers, training them on a new set of data for which you may only have a few hundred images. The result is a trained network that performs with significantly greater accuracy than if you’d started training from scratch. The reality is that a network trained from scratch would never catch up, no matter how long you trained it.

A key application is wafer metrology. Metrology involves monitoring your wafer process to make sure it’s staying within set limits by making measurements on the wafers over time. Trying to measure data on every wafer can be costly and cumbersome.

Virtual metrology (VM) is the prediction of wafer properties based on equipment settings and sensor data.  This data is used with real metrology data from a sample set of wafers to create a deep learning model that maps process data to wafer metrology parameters such as layer thicknesses, photolithography critical dimensions, and others. Instead of measuring every wafer, you can measure a sample set, and then use VM to predict the metrology performance of the rest.

As geometries shrink and capacity is increased, new wafer processing equipment is constantly brought on line, and it is a big challenge to generate enough training data to keep the deep learning models current. Transfer learning enables you to build up a network that’s been trained on many different types of equipment. When a new piece of equipment is added to the line, you can tune a pre-trained network to operate with only a small set of data collected on that new piece.

Q. This is a fascinating subject. What other kinds of deep learning are there?

A. Reinforcement learning involves training a deep learning network on which actions will achieve the best ultimate reward. In this case, the network is like the brain of a mouse learning the fastest path through a maze to get to the cheese – it learns to navigate complex problems and come up with the optimal solution. An example is using deep reinforcement learning for production scheduling. Let’s say you’re trying to figure out how to minimize the overall time it takes to work through a complex multi-step production process from start to finish – the network will try different types of scenarios and figure out what works best. 

Unsupervised deep learning has great potential for semiconductor manufacturing and test applications. Instead of telling the network what kind of data you’re giving it, you feed in unclassified data, and the network identifies things it sees that are similar to each other. It doesn’t know what those things are, just that they’re similar. It trains itself to classify things that look alike. This is powerful because you can throw a lot of unlabeled data at the network, and it will be able to identify relationships and act on them. It can find hidden relationships that humans might not have thought of, so unsupervised DL can do things that supervised DL can’t.

Advantest is working with university teams to investigate these techniques in detail, and we’re in discussions with multiple customers about ways to apply AI. We view it as a vital competitive advantage going forward.

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Posted in Featured Products, Uncategorized

High-Resolution Audio Requires Advanced Measurement Capabilities  

By Takahiro Nakajima, Senior Expert, Analog/Mixed-signal, Advantest Corp.

Smartphones supporting High-Resolution (Hi-Res) Audio are growing more widely available, enabling consumers to experience high sound quality when streaming music, movies or other content. To accommodate High-Res Audio, these devices integrate an increased number of power management ICs (PMICs) equipped with digital-to-analog converters (DAC), which require high dynamic range testing with 24-bit resolution.

This has, in turn, led to manufacturers’ increased demand for automated test equipment (ATE) with analog performance exceeding a total harmonic distortion (THD) of -130 dBc*, as well as the ability to perform 16 multi-site tests. This article details a solution for achieving both ultrahigh dynamic range performance and 16 multi-site testing.

Figure 1 shows a block diagram of a smartphone. Smartphones incorporate numerous semiconductors to drive power management, connectivity, sensors, displays, audio, cameras, and memory. In recent years, there has been a trend toward integrating the PMIC and audio coder/decoder (CODEC) into a single chip, as the figure illustrates. There has also been an increase in 24-bit resolution DAC, needed for support of Hi-Res Audio.

What is Hi-Res Audio?

The Hi-Res Audio specification – defined by the Japan Electronics and Information Technology Industries Association (JEITA) – allows a much wider dynamic range than that provided by CDs. A Hi-Res sound source, such as 24 bit / 96 kHz or 24 bit / 192 kHz, is converted to data at a finer resolution than a CD sound source (Figure 2), so it has much more sound information compared to a CD sound source. This means that Hi-Res Audio is as close as possible to the original sound, enabling the listener to experience sound quality comparable to being in a studio or concert hall.

Audio testing

The four test methods required for audio devices are the tests for total harmonic distortion (THD); total harmonic distortion + noise (THD+N); dynamic range (DR); and signal noise ratio (SNR). Each of these tests determines various requirements associated with Hi-Res Audio, and together they create a set of parameters that must be met in order to assure the highest quality audio performance.

 Once these tests are completed, frequency weighting is used to obtain measurement values matching the sensitivity of the human ear. The frequencies people hear the best are in the range from 2 to 4 kilohertz (kHz), and sensitivity declines at frequencies that are higher or lower.

A-weighting is commonly used for the weighting network. SNR/DR tests often show analog performance when A-weighting is applied.

Measurement error occurs when measured noise can be calculated from the difference between device performance and measurement instrument performance. For example, if the difference between device performance and measurement instrument performance is 0 dB, the measurement error is 3 dB. If the difference is -5 dB, measurement error is 1.19 dB. This clearly indicates that the better the performance of the measurement instrument, the lower the measurement error.

Advantest solution

The T2000 supports three Mixed-signal modules (GPWGD, BBWGD,8GWGD) as shown in Figure 3.

Advantest has developed a measurement technique with ultrahigh dynamic range to achieve industry-leading levels of analog performance for 24bit DAC solution, by adding high-precision analog circuits such as a band elimination filter (BEF) at the front-end of its T2000 general purpose waveform generator digitizer module (GPWGD).

 The target performance for the T2000 solution was set to be 5dB better than target device performance in order to enable analog measurement with higher precision from characterization to mass production (Table 1). The test results performed indicated that the T2000 Integrated Power System (IPS) + GPWGD solution can address multiple challenges associated with Hi-Res audio testing, including high dynamic range measurement, power supply/GND design and isolation, high multi-site testing.

Mobile PMICs require digital, high-precision mixed-signal/analog, and power testing. As a product for automotive/industrial devices and PMICs, the T2000 IPS system can have a number of modules installed, as shown in Table 2. A high-precision analog function can also be added to the front-end of the GPWGD as a 24-bit DAC solution for Hi-Res Audio. For semiconductor manufacturing pre-processing, a wafer prober, probe card, and pogo tower can be combined together. The analog circuits can be equipped with 16 channels by mounting additional analog circuits in the user area on the wafer prober.

Measurement results

On the T2000 platform, analog performance was demonstrated with an ultra-high dynamic range, showing that the platform can achieve results beyond the target performance – as occurred when all of the audio tests listed earlier were conducted. Moreover, the results are consistent and repeatable, as indicated in Figure 4. When measurements were performed 200 times continuously with 16 multi-site tests, a typical THD result of -134 dBc was consistently obtained.

The results detailed in this article indicated that twice the number of multi-site tests can be achieved compared to conventional systems when the T2000 is combined with an IPS and GPWGD module. This makes it possible for the solution to support everything from characterization to mass production for PMICs associated with Hi-Res Audio. Future test efforts will take on the challenge of solutions for 32-bit DACs that require a higher dynamic range.

* dBc = decibels relative to the fundamental carrier power level; standard measurement for total harmonic distortion (THD)

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Posted in Upcoming Events

VOICE 2019 Discounted Registration Available Through March 8

Scottsdale Program to Feature Keynote Speeches by Mentor’s Dr. Wally Rhines and Leader of the Bionic Age Dr. Hugh Herr

The Advantest VOICE 2019 Developer Conference will be held in two new locations – Scottsdale, Arizona on May 14-15 and Singapore on May 23 – under the unifying theme “Measure the Connected World and Everything in It ℠”. Online registration opens soon with a 20-percent discount offered for the Scottsdale event through March 8. As in past years, the focus of VOICE will continue to be the learning and networking opportunities offered through technical sessions, kiosk showcases, keynote speeches, the partners’ exposition and social events.

On May 15 at VOICE in Scottsdale, the program will begin with a keynote speech by Dr. Wally Rhines, CEO emeritus of Mentor, a Siemens business, whose innovative electronic design automation (EDA) products and solutions help engineers conquer IC design challenges. Dr. Rhines is a recognized spokesperson for the semiconductor and EDA industries.

Dr. Wally Rhines

Dr. Hugh Herr, professor and leader of MIT’s Center for Extreme Bionics, will follow with his keynote address on “The New Era of Extreme Bionics.”  Dr. Herr is not just developing smarter, more capable bionic limbs, he is redefining human potential and designing a world in which technology erases disability.

Dr. Hugh Herr

In addition to the early registration discount, group discounts are available to attend VOICE 2019; email mktgcomms@advantest.com for details. Those interested in attending the Singapore event should email mktgcomms@advantest.com for registration information.

Registered Scottsdale attendees are encouraged to make their hotel reservations at the Boulders Resort & Spa before the discount ends on April 10. For additional hotel information and to make reservations, visit the VOICE website.

A limited number of opportunities are available in both locations for companies interested in sponsoring VOICE 2019. Contact Amy Gold at amy.gold@advantest.com to learn more.

VOICE 2019 Quick Links

Registration

Keynotes

Sponsorships

Hotel Reservations

Questions: mktgcomms@advantest.com

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Posted in Uncategorized

New Solution Available for System-Level Testing of Advanced, High-Speed Semiconductor Memories for Mobile Applications

Advantest unveiled its new T5851 STM16G memory tester for evaluating high-speed protocol NAND flash memories including UFS3.0 universal flash storage and PCIe Gen 4 NVMe solid-state drives (SSD), both of which are expected to be in high demand for the LTE 5G communications market.

The mobile and automotive communication markets are booming.  It is estimated that soon almost all NAND memory in smart phones will use high-speed serial protocol interface controllers such as PCIe and UFS, the majority of which will require system-level testing (SLT).  In addition, shipments of UFS memories are expected to nearly triple in the next three years and surpass embedded multi-media cards (eMMC), the current market leader.  By 2021, more than 800 million total eMMC, UFS and NAND smart phone units will be shipped, according to the market research firm IHS Markit.

The new T5851 STM16G system’s multi-protocol architecture makes it suitable for testing all SSDs with ball grid arrays (BGA) or land grid arrays (LGA) in both engineering and high-volume production environments.  Using one common platform reduces deployment risks while the system’s modular upgradability enhances users’ return on investment.

The universal, extendable platform has the versatility to test multi-protocol NAND devices with speeds up to 16 Gbps. The system’s tester-per-DUT architecture supports the test flows required for fast SLT of up to 768 devices in parallel.

The configuration and performance of the T5851 STM16G can be optimized for any generation of devices. Advantest’s FutureSuite™ software ensures that the new tester can be easily integrated with all other members of the T5800 product family.

As additional benefits, the new memory tester can be combined with Advantest’s M6242 automated component handler to create a turnkey test cell, it has a liquid-cooling system for reliable thermal management and it delivers superior reliability.

Shipments to customers are scheduled to begin in the second quarter of calendar 2019.

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