gosemiadmin | Go Semi and Beyond

Home » Posts by gosemiadmin

Advantest’s New TS9001 Time Domain Reflectometry (TDR) System Employs Terahertz Technology to Provide High Resolution Analysis of Circuit Faults

Advantest Corporation announced that it has initiated sales of its new TS9001 TDR System. The new system fully utilizes the company’s unique terahertz technology to enable non-destructive and high-resolution analysis on circuit faults in advanced semiconductor packages, such as flip chip BGAs, wafer level packages, and 2.5D/3D ICs.

The TS9001 TDR System provides semiconductor manufacturers with flexible solutions for addressing a variety of failure analysis requirements. By establishing a low-cost failure analysis environment and enabling connections to high-frequency probing systems already in use by customers. TS9001 offers customers one of the shortest measurement times on the market.

Advantest’s leading-edge semiconductor test technology and terahertz failure analysis technology supports the development of innovative semiconductor supply chains, while enhancing the customers’ quality control.

Background

As semiconductor packages (hereafter, devices) grow smaller and more highly integrated, the ability to locate failures with non-destructive, high-resolution technology is increasing in importance. Providing access to the industry’s most advanced failure analysis environment is critical to being able to address the wide variety of failure analysis issues that are present in these complex devices. To meet these requirements, Advantest developed the TS9001 TDR System, which enables customers to direct-connect their high-frequency probing systems, to obtain high-speed, high-resolution measurement.

Key Features

High-speed and high-resolution measurement

The TS9001 TDR system, which utilizes an ultra-short pulse signal processing technology, achieves higher distance-to-fault resolution of 5 μm and precise fault location identification with the industry’s fastest class measurement time of 30 sec (Number of integration: 1024, 1/10 shorter than our conventional products). This is the same proven technology used in our ground-breaking terahertz analysis systems.

Versatile connectivity for high-frequency probing systems

TS9001 can be configured with a high-frequency probing system owned or selected by the customer. It offers flexible solutions according to the device forms or fault analysis environments.

(1) Failure analysis of devices with micro bump

By connecting the TS9001 to a high-frequency probing system along with a high-resolution microscope, failure analysis of devices with micro bump of minimum diameter 50 μm is possible.

(2) Temperature control function

Failure analysis of devices kept in low/high temperatures is also possible, if the system is connected to a high-frequency probing system with a thermal-system function.

(*) TDR (Time Domain Reflectometry) is widely used to locate circuit failures. Input pulsed signals are reflected at circuit faults inside the device. Time domain analysis of the reflected waveform　allows users to determine the fault location and failure mode (open or short) by waveform comparison between good device and failed device. The peaks appearing only in the failed device are analyzed to identify them.

For more information on this system, visit our Website.

URL: https://www.advantest.com/products/terahertz-spectroscopic-imaging-systems/tdr-option

Posted in Featured Products

New Memory Tester Integrates Burn-In and Core Testing for 5G Product Development

Advantest has added to its H5600 family of memory testers by introducing the new, highly versatile H5620ES engineering test system, designed for both high-speed burn-in and core testing of today’s DDR4, next-generation DDR5, and low-power, double-data-rate (LPDDR) devices in laboratory environments. By streamlining the number of accessories and reducing the time required between burn-in and core testing, the new H5620ES shrinks the cost of test for evaluating advanced memory devices used throughout 5G applications. The new system ably addresses all barriers to cost-efficient development and qualification of the newest data-storage ICs that are in high demand for the rapidly growing 5G market.

Like its sister system, the H5620 production unit introduced in March of this year, the new tester delivers high productivity by parallel testing both DDR4 and DDR5 memories. It can accommodate memory ICs with 100-MHz frequencies and 200-Mbps data rates.

The engineering system is optimized for ease of use in product development, enhancing testing efficiency in the lab prior to production. Its compact design saves space and enables mobility in laboratory environments while its open-top architecture makes it easy to perform pick-and-place operations without removing the device interface board (DIB).

The H5620ES runs on the same FutureSuite™ operating system as the H5620 production unit, enabling testing with the same waveform. It also allows pre-testing routines such as contact checking to be conducted on the H5620ES system before transfer to the H5620 tester, thereby reducing cycle times in production.

Posted in Q&A

Q&A Interview: Moving Test to the Fast Lane

By: GO SEMI & BEYOND Staff

In this issue, our Q&A interview subject is Steve Pateras, Senior Director of Test Marketing for Synopsys. Steve provides a look at a new test capability, jointly developed by Synopsys and Advantest, that leverages high-speed communication interfaces such as USB and PCIexpress to improve test throughput. (NOTE: This piece was originally intended to serve as a preview of Steve’s VOICE 2020 keynote address; although canceled this year, the conference will return in 2021, as will Steve.)

Q: What was the catalyst for developing this approach?

A: The industry is always looking for new ways to improve test throughput, in order to reduce test times and costs. As chip designs get larger and larger, you need more test data, so to keep test costs in line, you need to improve bandwidth to get better throughput.

Moore’s Law kept things growing and increasing in complexity over the past several decades, but periodically, fundamental paradigm shifts needed to happen. The first was in the 1980s, when we moved to structural test because chips had become too complex to cover all possible failure modes using functional verification. Looking only at the I/Os related to flip-flop scan chains, rather than every functional I/O, became the new norm, and this worked well for a couple of decades.

By 2000, scan alone had become inefficient – the number of scan chains and I/Os to scan kept growing larger and larger, and the sheer volume of data was too massive to store on the tester. This led to the next paradigm shift: compression channel I/O. Data is compressed on the tester, then sent to the chip, where it is decompressed on-the-fly into multiple scan chains. Again, this reduced the number of I/Os and test times to a manageable amount. Another 20 years passed, which brings us to today.

As chip features shrink down to 14nm, then to 7nm and beyond, we’re still seeing exponential growth in the numbers of patterns and pattern test data. We’ve again reached the point where we can’t accommodate the volume – even compressed, there is too much data to be stored, and it takes too long to scan data in and out. It’s time for a new approach.

Q: You’re talking about the next paradigm shift?

A: Exactly. Structural (scan) patterns form the primary test for digital logic – more patterns are required to maintain quality, with larger designs requiring more manufacturing tests, and new process nodes demanding advanced fault tests. At some point, things start to break; how do you achieve the necessary bandwidth when you have limited tester speeds and a limited number of available pins? Figure 1 shows real-time bandwidth limitations – that is, the actual number of gigabits you’d need to test some of the newer, larger devices. Existing approaches can’t accommodate moving from tens to hundreds of gigabits per second, let alone into the terabit range.

Figure 1. As data volumes increase with device complexity, test times rise sharply.

What we’ve been developing with Advantest is the use of high-speed functional I/O (HSIO) to increase bandwidth. Instead of feeding the compression logic onto the chip via dedicated scan I/O, we’re using very high-speed serial functional interfaces, i.e., USB and PCIexpress, to achieve this. Once the data is entered, we can convert it into the parallel data we need to feed the compression logic. We use these very high-speed serial inputs to get the required bandwidth, and then we parallelize this widely to all the many parallel scan chains on the chip.

Q: How is the parallelism achieved?

A: Via the on-chip logic that we provide, which works essentially like a transformer. It allows for very large amounts of data coming without the need for dedicated, lower-speed I/Os. We’re essentially reusing the high-speed interfaces that exist on virtually every chip today. Instead of reinventing the wheel and adding more dedicated pins per test, we simply piggyback on top of these interfaces during the test process to send high-speed test data through them [Figure 2].

Reusing these existing high-bandwidth functional interfaces offers three key benefits: it reduces test time; it eliminates the need for dedicated test I/O; and it provides test portability through the product lifecycle.

Figure 2. Reusing HSIO protocols improves scan bandwidth, significantly lowering test times.

Q: How long has the new solution been in development, and what does it entail?

A: We’ve been working with Advantest on this new HSIO paradigm for over two years, combining key components from our TestMAX suite of software with Advantest’s V93000 SoC tester. The solution entails three key aspects, summarized in Figure 3:

Packetizing manufacturing test data to accommodate HSIO protocols. Integrated into the V93000, our software [dark green box] takes traditional parallel data from ATPG tools, converts it into high-speed packet data, then depacketizes the data coming back and maps it to known failure descriptions.
Enabling the tester to accommodate this approach [light green box]. Testers themselves need to be able to drive data through these high-speed interfaces, so through this joint effort, Advantest has added new hardware onto the V93000 to provide the HSIO function and ensure their SmarTest software can work with it.
Ensuring the chips can handle this high-speed packet data. We devised a bidirectional HSIO-to-DFT interface controller, which is added to the chip as IP [dark grey box] to actively manage incoming high-speed packet data on one end and receive the parallelized lower-speed test data on the other.

Figure 3. The new HSIO test paradigm integrates key software, hardware and on-chip functionality.

In addition, our Adaptive Learning Engine (ALE) adds more intelligence to the test process. It allows our software to actively look at failure data coming back from the device and adapt the test to deal with the kind of failures that are being seen on the tester, as well as perform more advanced diagnostics. This can be performed locally on individual testers, as well as on a Big Data level – each tester on the floor can send its results to a centralized analytics engine analyzing results and looking for systematic issues across multiple devices over time. In this way, we can help to greatly improve the test process at the test-floor level.

For more details, real-world examples and updates on this new high-speed functional I/O test paradigm, make plans now to attend Steve’s keynote address at VOICE 2021 in Scottsdale, Ariz.

Posted in Top Stories

High-Volume Production Test of AiP Modules for 5G Applications

This article is a condensed version of an article published in the May-June 2020 issue of Chip Scale Review, p. 20. Adapted with permission. Read the original article at http://fbs.advantageinc.com/chipscale/may-jun_2020/22/.

By Jose Moreira, Senior Staff Engineer, SOC R&D, Advantest

The arrival of 5G promises enhanced mobile broadband (eMBB), massive machine-type communication (mMTC), and ultrareliable low-latency communication (URLLC). But as 5G rolls out, the test community faces challenges and opportunities. That’s particularly true regarding the antenna arrays that will connect handsets to base stations.

5G New Radio (5G NR) defines two ranges, frequency range 1 (FR1) and frequency range 2 (FR2). FR1 includes the sub-6-GHz frequencies in use for previous generations of cellular technologies, but FR2 opens up mmWave frequencies above 24 GHz for 5G deployment. 5G NR leverages the FR2 frequencies to achieve larger modulation bandwidths (for example, 800 MHz). However, the high transmission losses at these frequencies require the use of antenna arrays for multiple-input and multiple-output (MIMO) functionality and to focus the transmission beam (beam forming) in both the base station and the consumer’s handset. These arrays come in the form of antenna-in-package (AiP) modules.

For the handset, these AiP modules will usually have an array of dual-polarized patch antennas for top firing and, in some instances, an array of dipole antennas for side firing (Figure 1).

Figure 1. This example of a generic antenna array module comprises 12 dual-polarized patch antenna elements and seven dipole antenna elements.

To minimize RF losses to the antenna radiators, the AiP modules include RF integrated circuits that provide modulated mmWave signals to the AiP antenna array with the needed gain and phase to each radiating element. The modules then usually only require power, digital control signals, and modulated intermediate-frequency (IF) signals.

AiP modules for 5G handsets must be small to fit into the modern cellphone form factor, and multiples of them need to be used in a single cellphone because the user’s hand position has a significant impact on the transmitted beam loss. Also, the AiP modules in a cellphone might not be all equal, but in fact have different antenna configurations depending on the handset design.

Regardless of configuration, these AiP modules must be tested. The 3GPP standard defines three methods for the over-the-air (OTA) standard compliance testing of AiP modules: direct far field, indirect far field, and near-field to far-field transformation. Each of these methods have advantages and disadvantages, but they all require relatively large test chambers and a complex manipulator to rotate the AiP device under test (DUT) or the measurement antenna.

These methods are neither practical nor necessary for high-volume production testing, where the objective is to check the functionality of the antenna under test (AUT), not its compliance. Low cost of test is critical because most of the end applications are consumer oriented. Also, to keep costs down it is important to reuse as much as possible the test-cell infrastructure already deployed for testing RF integrated circuits.

This paper presents three possible options for the production OTA testing of AiP modules with ATE: far-field testing, radiating near-field testing, and reactive near-field testing. The book Theory and Practice of Modern Antenna Range Measurements¹ provides details on the transition from the near field to the far field. For the purposes of this discussion, it suffices to note that there is no hard boundary between near and far field, but a continuous transition where the radiated waves become locally more planar as they propagate away from the radiating antenna. From an antenna-measurement perspective, the far-field region is the best because the radiated waves are locally planar, and the measurement antenna is too far away to have an impact on the AUT.

But the far-field distances also imply large dimensions for the measurement setup, and radiating and reactive near-field testing approaches offer more compact alternatives.

Figure 2. These examples of OTA ATE far-field measurement setup show a motorized linear stage (left) and a static setup (right).

OTA far-field testing

Figure 2 shows two examples of a simple far-field measurement setup on an ATE system. This approach is excellent for an initial start with OTA testing on ATE because one can start in the safety of the far-field measurement range while doing correlation and debugging of the AiP DUT using the ATE system. Calibration on a far-field setup is also trivial using standard antenna measurement calibration procedures1. The problem arises when considering high-volume production by integrating a far-field OTA methodology on a standard ATE test cell.

The mechanical dimensions required for a far-field OTA test solution prevent the usage of standard ATE test-cell commercial handlers, thereby requiring custom robotic handlers and creating additional costs. Cost reduction through multisite implementation on ATE is also nontrivial with a far-field OTA ATE implementation.

OTA radiated near-field testing

One approach to integrating an OTA measurement setup into a standard ATE test cell is to move the measurement antenna into the radiating near-field region. Figure 3 shows low-cost radiating near-field test sockets for a patch-type antenna array AiP. In this example, the measurement antenna is 11 mm from the DUT AiP antenna array. A radiating near-field antenna test has the advantages of easy integration within a standard ATE test cell along with easy multisite implementation.

Figure 3. These examples of low-cost radiating near-field OTA sockets support manual ATE-based OTA testing.

Because in a production test environment the objective is to identify failed AiP modules and not to characterize them, one could assume that there would be some easy correlation between good AiP modules tested in a far-field setup with failing AiP modules tested on a near-field setup, assuming a comprehensive list of performed tests. This is a valid thinking, but one needs to be aware of two important drawbacks on a radiating near-field measurement setup. The first is that the measurement antenna is now so close to the AiP DUT antenna array that it will have an impact on the DUT AiP antenna elements (antenna detuning) and can even result in a standing-wave effect.

The second drawback is shown in Figure 4.

Figure 4. In this example, the distance from the measurement antenna to the different antenna array elements on an AIP DUT differs.

Because only one measurement antenna is used, depending on the DUT AiP antenna array geometry, the distance of each DUT antenna array element to the measurement antenna will be different. This can have a significant impact on a worst-case scenario^2,3. Finally, calibration in the radiating near-field is nontrivial. If a golden-device calibration is used, results are critically dependent on the golden device’s performance, and absolute measurements are not possible.

OTA reactive near-field testing

An alternative is to measure the DUT AiP antenna array in the reactive near field. In this case, a classical measurement antenna cannot be used because in the reactive near-field range it would have a dramatic effect on the DUT AiP antenna elements. To measure on the reactive near field, the antenna or probing element needs to be very small. Figure 5 shows one reactive near-field probing concept for OTA ATE that has been patented by Advantest using two very thin parallel needles to probe the electric or magnetic field on the DUT AiP reactive near field. The main advantages are that each element of the DUT AiP array is individually measured (power and phase) and that the probe size is very small to minimize the disturbance of each radiating element. This concept is explained in more detail in other papers^4,5.

Figure 5. This near-field probing concept for OTA ATE uses two very thin parallel needles to probe the electric or magnetic field on the DUT AiP reactive near field.

Figure 6 shows an example of a prototype reactive near-field socket3. Here, measurement of a dual-polarized 2×2 AiP array results in eight individual signals. To keep ATE resources to a minimum, a solid-state relay switches each of the antenna/polarization signals in series to the ATE measurement instrument. A parallel measurement approach is also possible but requires eight ATE measurement instruments. The optimal setup will depend on a detailed cost-of-test analysis.

Figure 6. In this prototype reactive near-field socket, a dual-polarized 2×2 AiP array is measured resulting in eight individual signals.

Summary

For OTA testing with ATE of AiP modules, there is no right or wrong answer. Depending on the testing requirements and testing stage (for example, initial ramp-up or mature high-volume manufacturing), the OTA test strategy might be different. Figure 7 shows a high-level comparison of the different OTA test strategies presented in this paper.

In a future paper we will use a custom-designed 28-GHz 2×2 path antenna array in a 0.4-mm-pitch BGA package to compare the different approaches in terms of OTA measurement results with the Advantest V93000 Wavescale Millimeter CardCage ATE system.

Figure 7. This chart shows the advantages and disadvantages of three OTA test strategies in an ATE environment.

ACKNOWLEDGEMENTS

We would like to thank Natsuki Shiota, Aritomo Kikuchi, Hiromitsu Takasu, Hiroyuki Mineo, Sui-Xia Yang, and Frank Goh from Advantest for their support and collaboration on the OTA project development. We would like also to thank Prof. Jan Hesselbarth from the University of Stuttgart.

REFERENCES

Clive Parini, et al., Theory and Practice of Modern Antenna Range Measurements, IET, 2014.
Jose Moreira, Jan Hesselbarth, and Krzysztof Dabrowiecki, “Challenges of Over The Air (OTA) Testing with ATE,” TestConX China, Shanghai, October 29, 2019.
Natsuki Shiota, Aritomo Kikuchi, Hiroyuki Mineo, Jose Moreira, and Hiromitsu Takasu, “Socket Design and Handler Integration Challenges in Over the Air Testing for 5G Applications,” TestConX 2020, May 2020.
Jan Hesselbarth, Georg Sterzl, and Jose Moreira, “Probing Millimeter-Wave Antennas and Arrays in their Reactive Near Field,” 49th European Microwave Conference, 2019.
Utpal Dey, Jan Hesselbarth, Jose Moreira, and Krzysztof Dabrowiecki, “Over-the-Air Test of Dipole and Patch Antenna Arrays at 28 GHz by Probing them in the Reactive Near-Field,” To be presented at the 95th ARFTG Microwave Measurement Conference, August 6, 2020.

Posted in Top Stories

Wave Scale RF8 – Enabling the Next WAVE in RF Communications Test

By Dieter Ohnesorge, Product Manager, RF Solutions, Advantest Corp.

Over the years, Advantest has remained at the forefront of test innovation through close collaboration with customers and partners, and by keeping our finger on the pulse of industry and market trends. We launched the Wave Scale family of test cards for our V93000 system-on-chip (SoC) test platform just over four years ago, and in that short time, we have greatly expanded the line with new products designed to meet burgeoning test demands – e.g., Wave Scale RF, Wave Scale MX, and Wave Scale Millimeter.

The test economics of state-of-the-art smartphones, tablets and routers demand highly parallel RF test. Now, we are addressing this next wave in RF communications test, enabled by Wi-Fi 6E, operating in the 6GHz band and coming up to 7.125GHz. This forthcoming update to the Wi-Fi standard will extend the features and capabilities, including higher performance, lower latency, and faster data rates—for this higher band. Our new Wave Scale RF8 card enables parallel test capabilities for Wi-Fi 6E, as well as for 5G-NR transceivers, LTE-Advanced Pro and internet of things (IoT) devices.

The extension to Wi-Fi 6E will make available 1200MHz of additional bandwidth in the unlicensed frequency spectrum (see Figure 1). Compared to these 1200MHz, the 2.4GHz band has just three non-overlapping channels with a total bandwidth of 60MHz, and is already crowded with multiple users competing for bandwidth. Even with 25 channels and an additional 500MHz of bandwidth, the 5GHz band gets filled up quickly – a problem that has become even more apparent with many people in close proximity tapping into Wi-Fi to work in from home or attend school remotely.

Figure 1. The chart illustrates the importance and benefits of Wi-Fi 6E. Wi-Fi at 2.4GHz uses 60MHz total bandwidth with up three non-overlapping channels, while the 5GHz band adds 500MHz and up to 25 channels. Wi-Fi 6E now adds a massive 1200MHz to the existing Wi-Fi bandwidth, adding up to 59 additional channels.

With the 6GHz band, however, comes added channels and a substantial extension of 1200MHz in usable bandwidth. Moreover, all three bands can be used simultaneously – e.g., users can read and send email in the 2.5GHz band, place Wi-Fi calls in the 5GHz band, and download streaming content in the 6GHz band. Good news for users, this nevertheless creates new challenges with respect to testing these communication devices.

Wave Scale RF 8 is capable of both highly parallel multisite and in-site parallel testing, providing a new dimension of test coverage and economics. Testing both the send and receive channels takes a fraction of the time that would be required using a traditional test flow, and it can perform high multisite testing using native ATE resources, all within the V93000 test head. Advantest is the first in the industry to enable such high multisite parallelism for these applications, providing an unmatched test time benefit (see Figure 2).

Figure 2. The benefits of massively parallel test are illustrated here. Stacking tests test in a parallel test flow rather than one-by-one serial test drastically reduces test times; parallel mission-mode tests are reduced by up to 50%.

The card’s RF-optimized architecture comprises four complete RF subsystems to achieve high-throughput testing. Within each subsystem is an independent modulated source, a waveform generator/digitizer, scattering parameters, and a test processor that can make multiple RF measurements in the shortest possible time. Each card includes 32 RF ports, true parallel stim measurement ports, and – as mentioned earlier – operates at up to 8GHz with a modulation bandwidth of 200MHz. Its wide-frequency capability is a vital aspect of Wave Scale RF8 – the Wi-Fi6E standard can actually go up to 7.125GHz, so is well covered by the 8GHz capability of the Wave Scale RF solution.

Continually staying ahead of the industry curve is an important aspect of Advantest’s brand promise to our customers. We focus on having the solution in place that customers will need in order to adapt to new test requirements. With Wave Scale RF8, we have made sure that we can accommodate the massively parallel testing that advanced communications devices demand. With multiple independent subsystems in a single card, Wave Scale RF8 delivers the cost-efficient production solution for next-generation Wi-Fi 6E and cellular devices.

« Older Entries

Next Entries »