Interview with Keith Schaub on the Challenges of Testing Today’s Complex Chips

This Q&A is adapted from an article posted to the Semiecosystem blog by Mark LaPedus. It details a conversation with Keith Schaub, vice president of technology and strategy, regarding the test challenges for today’s complex AI chips, gate-all-around transistors, chiplets, and 3D NAND. The original article can be found here.

Q: How has semiconductor test changed over the years?

A: IC test has undergone significant changes over the years, evolving alongside the increasing complexity of semiconductor devices. Initially, testing focused on basic functionality, but as devices grew more intricate, the need for more advanced testing methods emerged. The ATE industry responded by developing new, more capable testers to handle higher pin counts, faster speeds, and greater integration. There was also a shift from purely functional testing to structural testing, which provides deeper insights into the integrity of the chip’s design and manufacturing process. In recent years, system-level testing (SLT) has become increasingly important, enabling verification of complete systems and ensuring interoperability of components. Modern IC tests now include sophisticated techniques such as built-in self-test (BIST) and scan testing, enabling more thorough verification. Additionally, the rise of system-on-chip (SoC) and other advanced technologies has driven the development of testers that can handle multiple functions simultaneously. This IC testing evolution reflects the semiconductor industry’s continual pursuit of higher quality, performance, reliability, and efficiency.

Q: What challenges do you encounter when testing AI devices? 

A: Testing AI chips and accelerators presents several significant challenges due to their complexity and scale. These devices often feature large die sizes, billions of transistors, and dozens to hundreds of cores running at different speeds, depending on workloads. This variability increases the importance of advanced thermal management and control. Ensuring performance and reliability in such dense circuitry requires highly sophisticated ATE capable of handling high-speed interfaces and extreme thermal performance. Hotspots are a critical concern; not only understanding where they occur but being able to predict when they’ll occur during testing is vital for effective thermal control. Comprehensive validation is needed to ensure these chips perform optimally under diverse conditions, particularly in managing power densities and minimizing thermal hotspots. The integration of AI processors with other system components necessitates thorough SLT to verify overall system functionality and interoperability. Additionally, the rapid evolution of AI technology means testing methodologies must continually adapt to keep pace with new architectures and innovations. Overall, these challenges underscore the need for cutting-edge testing solutions to ensure the reliability and performance of AI semiconductor devices.

Q: Tell us more about system-level test. When do you use it in the test flow?

A: SLT is a comprehensive testing methodology used to validate the functionality, performance, and interoperability of semiconductor devices within their intended system environments. Unlike traditional testing methods that focus on individual components, SLT evaluates the entire system, ensuring that all integrated parts work seamlessly together under real-world conditions. 

Over the years, SLT has evolved from being an optional insertion to a mandatory step in the test flow, particularly for complex devices such as AI chips, processors, and SoC solutions, where multiple functionalities and high integration levels are involved. SLT is typically used in the latter stages of the test flow after initial component-level tests have been performed. It follows traditional tests like wafer sort, package test, and burn-in, providing an additional layer of assurance by verifying the complete system’s behavior. For example, in the case of an AI processor, SLT would involve running actual AI workloads and applications to ensure the chip performs correctly within the end-user system. This helps identify any issues related to power management, thermal behavior, and interactions with other system components that might not be detected during earlier test stages.

Q: What new challenges does the transition to gate-all-around (GAA) transistors present?

A: The transition to gate-all-around (GAA) transistors at the 3nm and 2nm logic nodes presents several new challenges for testing. GAA transistors offer improved performance and power efficiency compared to finFETs, but their unique structure and increased density introduce complexities in test processes. One of the primary challenges is ensuring accurate characterization and validation of these advanced transistors, as their electrical properties can be more sensitive to variations in manufacturing processes. Moreover, the increased device density at these nodes requires more sophisticated ATE with higher resolution and precision. Thermal management becomes even more critical due to the higher power densities, necessitating advanced thermal testing techniques to identify and mitigate hotspots. The integration of GAA transistors also demands enhanced DFT and BIST strategies to ensure comprehensive coverage and efficient testing processes. The rapid evolution of these technologies requires continuous updates to test methodologies to keep pace with the latest advancements in GAA transistor design and fabrication. Overall, while GAA transistors at 2nm and beyond promise significant performance benefits, they also necessitate advanced and adaptive testing solutions to address the new challenges they bring.

Q: What are some of the test challenges and ATE solutions for chiplets?

A: Chiplets are generating significant attention in the semiconductor industry due to their potential to enhance performance and flexibility in chip design. However, they introduce several unique test challenges, such as ensuring seamless integration and communication between multiple chiplets within a single package, requiring rigorous testing of interconnects and interfaces. Ensuring known good die (KGD) is critical, as a single defective chiplet can render the entire package unusable, leading to high costs. To address this, shift-left strategies are increasingly important, involving early and comprehensive testing during the design and pre-assembly phases, leveraging AI techniques to enhance test coverage and predict potential failures. The heterogeneous nature of chiplets necessitates highly adaptable ATE capable of handling diverse test requirements. Additionally, SLT is crucial to verify the functionality and interoperability of the combined chiplets under real-world conditions. Thermal management and power delivery are critical, as multiple chiplets within a confined space can lead to hotspots and power distribution issues. Advanced thermal testing techniques and power analysis are required to identify and mitigate these problems.

ATE solutions are evolving to provide higher channel counts, greater flexibility, and improved precision. DFT features, such as BIST and boundary-scan, are increasingly integrated into chiplets to facilitate efficient testing. Overall, while chiplets offer exciting possibilities for innovation, their successful implementation hinges on advanced and flexible ATE solutions, ensuring KGD and employing shift-left strategies enhanced by AI.

Early Detection of C-RES Degradation on High-Current Power Planes

By Brent Bullock, Advantest America Inc.

Probe-card or device contactor damage can be dramatic and catastrophic, with yield dropping drastically very quickly. What is not dramatic is the hypothesized slow probe needle or contactor degradation process that might precede catastrophic failure. Such degradation is difficult to detect in the early stages, when probe cards, die, and packages continue to yield normally. A key goal is to detect this degradation as soon as possible to avoid catastrophic damage without incurring yield loss or unnecessary equipment downtime. A related goal is to determine the root-cause scenarios that cause damage to probe needles or contactors.

Measuring contact resistance

One possibility for detecting the onset of probe or contactor degradation is to measure contact resistance (C-RES). This measurement can be accomplished by taking equipment offline, which also allows visual inspection of probe tips. This approach, however, thwarts the goal of minimizing downtime, and it provides limited insight into the root causes of failures—for example, it cannot determine what test sequences were running when a failure occurred. 

Low-current C-RES measurements are valuable, given uniform planarity with clean probe needles. For example, uniform C-RES changes will correlate between I/O pins and large VDD power planes, regardless of pin type (Figure 1, top). However, C-RES can be nonuniform because of particles, needle warpages, device contact defects, or other anomalies affecting a few pins. Unfortunately, low-current measurements cannot detect subtle changes in C-RES for a small percentage of pins isolated within large power planes, rendering nonuniform C-RES issues within large VDD planes unobservable on I/O pins (Figure 1, center). This limitation can be overcome by improving measurement granularity, taking measurements at higher current levels, or combinations of the two.

Figure 1. Probes can exhibit uniform (top) or nonuniform (center) planarity, and sub-gang measurements (bottom) can provide adequate resolution to detect anomalies in the latter.

Sub-gang measurements

One approach to improving C-RES measurements despite nonuniform contact problems is to take advantage of the fact that a VDD power plane is likely to be powered by multiple power-supply channels. The multiple channels allow sub-gang per-channel measurements that can provide sufficient granularity to detect C-RES variances with adequate resolution (Figure 1, bottom). For example, Advantest’s EXA Scale generation of instruments for the V93000 platform includes power supplies, digital comparators, and data converters (Table 1) that can discern C-RES variations between channels.

Table 1. Exascale instrument capabilities and specifications

EXA Scale instruments can determine C-RES by measuring the voltage drop (vDrop) across the probe head for a given measurement current. vDrop can be measured and recorded at a specific point in time or averaged over multiple points in time. This approach may require additional test time, and, similar to off-line measurements, it provides limited insight into the root causes of failures.

Monitoring vDrop

A better approach involves the monitoring of vDrop using continuous ADC sampling and the triggering of an alarm when significant C-RES anomalies occur. This approach has the added advantage of pinpointing what test sequences were executing during significant C-RES changes, thereby facilitating root-cause analysis. Figure 2 shows the XHC32 ultra-high-current power supply configured to provide such continuous monitoring of the C-RES values on both the VDD and VSS sides of the die. This approach requires an extended sense line, which must be added during DUT board design, in addition to the primary sense line.

Figure 2. An XHC32 extended sense line monitors the delta value relative to the primary sense line.

Advantest’s SmarTest ATE software includes a feature that facilitates the programming of the extended monitoring and alarm functions in either interactive or API modes. Figure 3 shows results with per-channel ganging granularity, initiated by checking the perPogo box in the instrument view (left). Data for each channel is shown on the right, with the highlighted channel showing a significant anomaly in measured current. To further control the ganging granularity, Advantest offers a capability called Ganged on the Fly dynamic master-channel switching, which is useful for changing the master sense line when the IR drop across a power plane varies with test content. The capability supports unique signal names for desired master-channel scenarios.

Figure 3. Checking the perPogo box in the instrument view (left) enables the display of per-channel results (right).

Measurement results and comparisons

Figure 4 shows actual waveform results, with the extended vDrop profile shown in blue and the current shown in yellow. Extended vDrop scales with the current flow, with capacitor charge/discharge cycles inducing transient variations. 

Figure 4. The extended vDrop value (blue) scales with current (yellow), with capacitor charge/discharge cycles inducing transients.

Figure 5 shows the extended vDrop and current values shown in Figure 4 converted to power (brown) and C-RES (blue) values, with C-RES impacted by device contacts as well as the probes. The conversion is part of Advantest’s new contact rating feature, which eliminates the issue of having to adjust for power, reducing engineering workload.

Figure 5. The brown and blue traces represent power and C-RES, respectively, derived from the voltage and current traces in Figure 4.

Figure 6 shows vDrop measurement trial data for two equipment setups A and B, which each have induced variations in the equipment and known variances in DUT contact quality. Measurements were taken for three separate tests, with each test performed four times, once for each of the two setups using the lower power Core Supply A and once for each of the two setups using the higher power Core Supply B. 

As shown in the figure, tests run on each setup using the low-power Core Supply A yield very similar results. For example, the measurements at the left of the Core Supply A results show that test 264 run on Equipment Setup A (Series 1) and the same test run on Equipment Setup B (Series 2) yield nearly identical measurements, making it difficult to draw inferences about C-RES variations. In contrast, the results for the same test run on the same two setups using the higher power Core Supply B are clearly distinguishable, demonstrating improved capability for vDrop measurements, and hence C-RES measurements, when utilizing currents that represent a higher percentage of total CCC.

Figure 6. Measurements taken with the lower power Core Supply A (left) and the higher power Core Supply B (right) show that the higher power supply provides improved capability for distinguishing C-RES variations.

Summary

Extended vDrop measurements can detect test-cell variations but have limited potential for isolating root causes of probe failures. In contrast, extended vDrop monitoring with alarm functionality is effective at detecting C-RES degradation, and because the monitoring is continuous, it is also effective in determining the root causes of the degradation—for example, test program sequences that may inadvertently apply too much current.

The implementation of vDrop monitoring requires planning because C-RES measurement or monitoring is not possible without proper routing, and the required extended sense lines must be designed into the DUT board. For the best results, retain the primary sense lines in the same location used for previous designs and add the extended sense lines on the opposite side of the die or contactor. Advantest offers the instruments and software necessary to implement extended vDrop monitoring and is performing additional work to automate the process of setting adaptive current clamp and vDrop alarm limit values.

AI Semiconductors Require an Integrated Test Solution

By GO SEMI & BEYOND Staff

The rapid proliferation of generative pre-trained transformers based on large language models (LLMs) is driving growth in the market for chips that can run the LLMs and other artificial intelligence (AI) and machine learning (ML) applications. Several types of chips hold promise for accelerating AI computing. Graphical processing units (GPUs) have proven to be capable solutions for the server/cloud environment, although work is underway on dedicated AI chips that could offer higher efficiencies. Edge applications will require lower-power devices, such as neuromorphic chips, which mimic neural network behavior. Personal computers are also gaining AI capabilities as chipsets appear to accelerate AI program execution without requiring cloud resources.

AI chip market

Research firms see a booming market for these AI-capable chips, although the exact numbers remain unclear because of the variety of classes of the devices. Mordor Intelligence forecasts that the market for GPUs will grow from about $65.3 billion in 2024 to $274.2 billion in 2029, driven by both graphics and AI applications. For its part, Gartner forecasts that worldwide AI chip revenue will increase from $53.4 billion in 2023 to $119.4 billion in 2027. Future Market Insights takes a longer look and forecasts that the AI chipset market will increase from $27.6 billion in 2024 to $287 billion in 2034—a CAGR of 26.4%. Deloitte puts the market for specialized chips optimized for generative AI at more than $50 billion in 2024, representing two-thirds of all AI chip sales during the year.Market.us surveys the complete global AI chip market, including GPUs, and estimates it is growing at a CAGR of 31.2% and reaching $341 billion in 2033.

Finally, as AI comes to the home and business desktop, personal computers will increasingly include dedicated chipsets that can accelerate AI computing, executing AI applications without requiring cloud connectivity. Canalys predicts that 60% of PCs shipped in 2027 will be “AI-capable,” up from 10% in 2023.

AI chip characteristics and test challenges 

The diverse classes of chips applicable to AI computing present unique test challenges, but several are common to most of them. For example, increases in device complexity are causing an explosion in scan-pattern depth, with pattern depths moving from what used to be a doubling every three years toward increasing tenfold every three years. Such growth necessitates new ATE technologies as well as the use of more efficient test data distribution schemes inside the device for higher throughput and parallel test of multiple cores.

The test flow for AI-enabled chips remains similar to that for traditional devices. Key stages in the flow include post-silicon validation, wafer acceptance test, wafer sort, final test, burn-in, and system-level test (SLT).

However, test-flow stages must become dynamically adaptable with real-time decision-making to minimize the cost of the test (COT), maximize yield, and facilitate dynamic failure analysis. In addition, test must occur in accordance with specific application requirements because scan testing exhaustively is becoming too expensive. Consequently, functional test content is moving forward in the flow in order to focus the valuable test time on the best parts. Additionally, binning must move from the performance-based approach of traditional test to an application-based approach that facilitates die matching (harvesting and smart pairing).

The dynamically adaptable test flow requires the seamless sharing of data across multiple test insertions and throughout the manufacturing process. It is also necessary to correlate behavior across insertions—to predict from a wafer-test result what will happen at future insertions, for example, and to identify defects before packaging.

Products and Services for AI chip test

Advantest offers a full lineup of test solutions for AI-capable chips that perform high-quality, cost-effective tests at high throughput. These platforms feature a module-based architecture that enables flexible reconfiguration of test modules to meet the ever-expanding list of test methods and applications.

In addition to the test platforms, Advantest offers associated equipment ranging from die-level handlers and thermal controllers to test-interface boards. In the handler and thermal-control category, Advantest provides the HA1200 die-level handler to support the test of singulated or partially assembled die. Equipped with Advantest’s ATC advanced thermal control option, the HA1200 enables known-good-die (KGD) testing of high-power, high-performance AI-capable devices within a thermal environment similar to their final assembly location. Testing in this fashion helps ensure true KGD for parts shipped in die form, chiplets, and large AI components that use back-side power delivery.

The company also offers an ATC 2kW solution for its M487x handler series to provide advanced thermal control at final test. Rounding out the hardware offerings from Advantest are high-performance DUT boards, test sockets, and thermal-control units, which accommodate very large form factor devices, including ones with coaxial electrical interfaces.

Advantest SLT and burn-in systems also provide a variety of thermal options to accommodate these large packages and high-power devices. These SLT thermal solutions include but are not limited to, active cooling and heating with fast dynamic response to maintain setpoints without overheating the DUT.

To handle the compute-intensive aspects of chip production and test, Advantest offers Advantest Cloud Services (ACS), which provide data management and analytics to pull together data from across the value chain. Included in ACS is Advantest’s ACS Real-Time Data Infrastructure (ACS RTDI) platform, which collects, analyzes, stores, and monitors semiconductor test data in a True Zero Trust security environment to enable customers to convert insights into actionable steps while protecting IP. In addition, the company’s ACS Edge platform can work in conjunction with Advantest’s platforms to handle computationally intensive workloads locally without loading down the test program or requiring cloud intervention. This addresses the growing industry need to run advanced, complex analytics at multiple test insertions while achieving very low and predictable latency.

Scan test

For scan test, the tester must efficiently move scan data in and out of the DUT. Test patterns must be deployed at the KGD testing step as well as at the final test of the complete heterogeneously integrated device. To accommodate tenfold pattern depth increases, testers require much greater memory depth. To meet this requirement, Advantest offers the Pin Scale 5000, which has multiple giga vectors per pin at up to 5 Gb/s.

Compression and memory pooling can scale this capacity significantly, either per pin or across multiple pins.

Some devices already require terabits of scan-pattern test data. Depending on the scan architecture, the available I/O speed, and the number of I/Os available for scan test, it can take many minutes to run a comprehensive scan pattern set on a very large device, which leads to high test cost and low throughput. As an alternative, a device’s native PCIe interface running at 16 Gb/s (with future versions moving to 32 Gb/s and 64 Gb/s) can also transport scan test data if the device-internal DFT supports it. To enable the use of PCIe or other serial interfaces, Advantest offers the Link Scale digital channel cards for the V93000 platform that enable software-based functional testing and PCIe (or USB) scan testing. Coupled with the latest generation of on-die scan data distribution networks, Link Scale can provide an order of magnitude faster pattern execution compared to traditional approaches. Alternatively, Advantest’s SLT and burn-in systems can utilize the same device-internal DFT and our controllers’ PCIe or USB interfaces to execute the same SCAN patterns that were generated for use on the V93000 Link Scale solutions. SLT and burn-in systems typically are less expensive per test site but run for much longer durations.

Power requirements 

The tester must also deliver sufficient power to the DUT while preventing overheating. Some devices are already drawing over 1,500 A, with future plans for 2,500 A and more, so controllability of the power resources is critical, requiring precise regulation, fast clamping capability, and in-line monitoring of contact resistance. In addition, supply voltages are being reduced from 1 V down to 750 mV, 600 mV, and even 500 mV. Each voltage drop requires higher accuracy. Power supplies must also be simple and flexible, enabling system configuration without buying more resources than needed.

To meet test power-supply requirements, Advantest now offers the XHC32 high current power supply for the V93000, which delivers up to 640 A per card and is an ideal complement to the widely used XPS256 universal power supply. Both cards feature digital regulation, fast clamp response, extended profiling capabilities, and state-of-the-art protection features for probe cards and sockets. In combination, they serve the needs of power-hungry performance digital devices for years to come. For our SLT and burn-in test cells, a similar power is available to each DUT in a highly parallel environment.

Scan and power requirements, taken together, have implications for multisite test as DUT pin counts vary. Scan port width may vary from tens of pins to hundreds of pins, and power requirements are constantly increasing. Bandwidth requirements for test data transmission greatly increase in parallel. Very large devices combining multiple dies in one package are also becoming increasingly prominent, especially in the HPC segment. As these chips have large numbers of I/Os, real estate on existing DUT boards is not always sufficient to accommodate all the external components required for test, especially in multi-site setups. The new DUT interface DUO available on the V93000 helps with this by significantly increasing the available space for large DUT interface boards while maintaining compatibility with existing DUT boards.

Boot-up and system-like test

In addition to scan and functional test, the tester must confirm that the chip meets its intended requirements for AI applications, such as object recognition. This level of testing requires DUT boot-up and execution of software on the DUT during the test insertion, which is typically performed during SLT. Interfaces such as PCIe are suitable not only for scan but also for the exchange of large amounts of data that would enable a chip to run a convolutional neural network or similar application. Boot-up sequences and interfaces such as PCIe can present fundamental problems that, if found only at SLT, impose significant time and cost issues for parts destined for heterogeneous integration.

To avoid these issues and to shift the boot-up test left, Advantest offers system-like test™ technology, which can help shift boot and other SLT content to wafer probe. Link Scale can alternatively act as a source of data, providing a data array for an AI processor.

Machine-learning driven test

And finally, Advantest is also leveraging ML to test ML-capable devices. The company has demonstrated test time and cost reduction using intelligent prediction from ML models. Customers with strong in-house data-science teams can develop similar models and run them on Advantest’s infrastructure. Advantest is continuously investigating AI-based methodologies to support its customers.

Table 1. Advantest products and technologies for AI-enabled chip test

Conclusion

As we step into the AI-driven future, the complexity of testing AI-enabled chips intensifies, marked by significant increases in test-data volumes and challenges related to heterogeneous packages with restricted access. Advantest is at the forefront of addressing these challenges with its robust portfolio (Table 1) of cutting-edge test hardware and sophisticated cloud-based services. Leading this transformative era, Advantest ensures its customers consistently remain on the leading edge of technology. By not only meeting today’s stringent demands for AI chip testing but also anticipating future needs, Advantest positions its partners for success. As AI reshapes industries and expands the horizons of possibility, facing the future of technology together with Advantest ensures your technology is always ahead and fully equipped to leverage the immense potential of the AI era.

Advantest Celebrates 25th Anniversary of Industry-Leading V93000 SoC Test Platform

Earlier this year, Advantest celebrated the 25th anniversary of its flagship V93000 system-on-chip (SoC) test platform. The V93000 revolutionized the semiconductor test industry with its single scalable platform approach, enabled by its test processor-per-pin architecture, which has endured over four generations. As a testament to this endurance, the very first V93000 system installed is still in use at the customer site in Italy, alongside several recently purchased fourth-generation V93000 EXA Scale testers.

 Upon its introduction in July 1999, the V93000 “quickly became a true landmark, as most top-end SoC testers after it would copy the system’s architecture for many years to come,” according to the Chip History Center. Since adding the V93000 to its portfolio when Advantest acquired Verigy in 2011, Advantest engineers have continually enhanced and expanded the V93000 scalable platform to offer a wide range of compatible tester configurations – from small-footprint engineering systems to very high-pin-count wafer sort and final test systems for high-volume manufacturing. The V93000 provides the industry’s broadest application coverage, including high-performance computing, artificial intelligence, RF, automotive and industrial, to name a few. The accompanying chart enumerates Advantest’s many advancements to the V93000 test platform over the years.

TechInsights Vice Chair and Senior Fellow G. Dan Hutcheson has long followed Advantest and the trajectory of the V93000 platform. “The V93000’s long life is an icon for the virtuous cycle that can be created when a team of tool designers thinks beyond the challenges of the day to develop an architecture that can evolve to address as-yet-unknown future challenges. In the case of the V93000, its long life has benefited both Advantest and its customers,” Hutcheson observed. Advantest has been named to TechInsights’ annual 10 BEST list for each of the 36 years that the market intelligence firm’s Customer Satisfaction Survey has been in existence.

“Technology evolves at a lightning pace, so reaching the quarter-century mark is a milestone achievement that underscores the value of our single, scalable platform approach,” said Juergen Serrer, senior executive officer and chief technology officer, Advantest. “Partnering with our customers to stay ahead of technology trends has enabled us to ensure that the V93000 platform stands ready, with state-of-the-art capabilities, to accommodate today’s and tomorrow’s test challenges. We look forward to what the next 25 years have in store.”