Data Collection and Analysis Drives Semiconductor Test in the Era of Chip Convergence

This article is a condensed version of an article published February 16, 2022, on JIWEI Net. Adapted with permission. Read the original article at https://www.laoyaoba.com/html/share/news?source=app_android_v2&news_id=806699&sign=5ab5d193a7e37db4e4b7728f73e6a208

In the Age of Convergence, many forces are driving continuous advancement of semiconductor testing technology. As more and more functions are carried on a chip, and technology grows more and more complex, the number and types of test steps must be multiplied – leading, in turn, to increased test costs. Semiconductor test equipment requires ultra-long “standby,” which is an asset-heavy investment in semiconductor manufacturing plants, with a life cycle of at least 5 to 10 years. In an intelligent world where chip technology and processes are rapidly upgraded and iterated, such equipment must be able to meet increasingly complex testing needs at any time.

As a result, test and measurement solutions must expand to address the entire semiconductor industry value chain. This includes not only the traditional “center” of testing (IC production processes, wafer test and final test), but also greater integration with IC design and more system-level testing (SLT) at the product level, plus connectivity, including the cloud, artificial intelligence (AI) and Big Data.

Advantest and PDF Solutions’ collaboration [first announced in July 2020], targets these expanded capabilities. By combining PDF Solutions’ Exensio platform and its Data Exchange Network (DEX) with Advantest’s advanced test equipment (ATE), customers can connect and analyze data anywhere in the semiconductor supply chain, helping them improve product yield and reduce test costs.

The two companies’ jointly developed product – ACS Dynamic Parametric Test (DPT) – integrates PDF Solutions’ Exensio data analysis products with Advantest’s V93000 parametric test system, enabling real-time optimization of parametric tests on the V93000 test platform and reducing manual interaction. The figure below illustrates the ACS DPT solution elements and functionality.

The balance of the article comprises an interview (also excerpted) with executives from both companies: Advantest’s Keith Schaub, vice president of strategy and technology, and Sonny Banwari, ACS vice president of business development; and PDF Solutions’ Guanyuan (Michael Yu), vice president of sales and operations, and David Park, vice president of marketing.

What are the key benefits of the Advantest-PDF collaboration, and why are they important for the semiconductor industry?

Keith:  Advantest has a long history in semiconductor testing, and we are the market leader in high volume manufacturing of semiconductor test products, with a range that spans from post-silicon validation, all the way to system-level test. Now, there is a lot of big data coming out of the test eco-system, and the industry has realized the future is using tools like AI and machine learning to mine data value, to improve the operational efficiency of the entire ecosystem, and of the entire supply chain.PDF Solutions is well established and strong in data analytics, and an ideal partner for bringing this advanced technology to the fore.

Michael: Advantest is the world’s leading supplier of semiconductor test equipment. Over the decades, it has amassed an enormous amount of knowledge and data related to semiconductor testing. PDF has always focused on data analysis of the entire semiconductor industry chain. The key point of this cooperation is to interconnect test-related data with the entire industry chain. For example, some data before testing, such as manufacturing-related data, can help to decide which devices to test and how to improve testing efficiency and quality. At the same time, data from these test cells can be brought forward to the subsequent steps of the supply chain and can also be fed back to obtain a more reliable and efficient test plan.

While the semiconductor industry is data-intensive, it is relatively backward in data analysis. What are the major obstacles? How will your joint data analytics-based products impact the industry?

Keith: The global semiconductor industry is in a period of rapid growth, and the huge market size brings huge growth opportunity for companies throughout the entire industry supply chain. At the same time, end-user applications are increasingly diverse and complex, with higher requirements for the quality and reliability of electronic components such as IC chips. Making test scheme coverage more comprehensive increases test cost. How do we control the cost of testing under the premise of ensuring higher quality? By mining the value of semiconductor data.

ACS powered by PDF Exensio is equivalent to providing the industry with an infrastructure platform for data analysis of the entire semiconductor supply chain. PDF Exensio can help collect data from semiconductor chip fabrication, test, and system-level test. With advanced algorithms, integrated workflows, and solutions delivered by ACS, more valuable information can be gained from the data generated by supply chain equipment and testing, resulting in shorter production times and higher overall equipment efficiency.

Sonny: As an example, the global chip shortage is a crisis for all industries, especially the automotive industry. In fact, this crisis has further forced carmakers to optimize products and technologies to deal with the chip shortage. The cooperation between Advantest and PDF Solutions is doing a similar thing: improving product yield through data analysis and providing customers with better products. It’s just reducing a company’s costs and improving its profitability, but it’s giving an opportunity for the entire semiconductor ecosystem to upgrade.

Michael: Indeed, to ensure the quality and reliability of chips, especially automotive chips, you need extensive testing, and that takes tremendous time and effort. But if we can adopt a traceable system and integrate the data of the entire production process, we can use AI and machine learning to tell us what to test, and what’s the most efficient way to perform the test. Instead of just one size fits all, with data analysis obtained through AI and machine learning, we can carry out personalized test plans for different quality requirements and find the best test results in the shortest time.

David: About five years ago, people were hesitant about going to cloud, mainly due to concerns about data security and privacy, especially in the semiconductor industry. This is the biggest obstacle for data analysis in the semiconductor industry. How to get enterprises across the supply chain willing to share data is a key step, and this is one aspect of what we are trying to do, to create a safe data sharing ecosystem. For example, both Advantest and PDF are involved in an initiative out of the GSA (Global Semiconductor Alliance) called TIES (Trusted IOT Ecosystem for Security), with the goal to bring together all the different players in the semiconductor supply chain, from design to manufacturing, packaging, and testing, to jointly form a secure trusted data sharing ecosystem.

Working remotely has also greatly promoted investments in cloud infrastructure, and the semiconductor industry is now a bit more open to moving data to the cloud. Being in the cloud will bring a more efficient and convenient data ecosystem to the entire semiconductor supply chain, for both scalability and computing performance.

In terms of empowering the semiconductor industry with intelligent means, such as big data analysis, cloud, and AI, what are the new trends in the future?

Keith: For a long time, the industry tended to use a one-size-fits-all general test solution, but different applications require customized test scenarios. However, with the increasing complexity of semiconductor process technology and the diversity of application requirements, the quality requirements for chips and other electronic components will also be different. Moreover, in the current environment of supply chain shortages, optimizing the test plan with different quality requirements for devices and use the big data analytics to control the test cost is vital. This is also what we are doing in cooperation with PDF Solutions.

Sonny: In the future, we will also increasingly tap the potential of AI-based and machine learning to develop more killer applications. Advantest and PDF understand each other, and we look forward to working together to elevate the power of machine learning to a new level in semiconductor testing and data analysis.

Michael:  As technology progresses, the manufacturing process becomes more and more complex; in addition, as chip size increases, there are more and more functions, which means that the amount of testing will also increase, and the whole process will generate an increased amount of data. And how to effectively leverage all of this data – through machine learning, AI, cloud computing and other methods, including data mining, to improve the overall efficiency of semiconductor manufacturing and optimize costs – will become more and more important.

Harnessing the Power of Data in Semiconductor Test

This article is a condensed version of an article published in the Winter 2021 issue of MEPTEC Report. Adapted with permission. Read the original article at https://issuu.com/mepcom/docs/meptec_report_winter_2021?fr=sNTRhZDE1OTk3NzE

By Ken Butler, Strategic Business Creation Manager, Advantest America

Every day, new methods are being developed to harvest, cleanse, integrate, and analyze data sources and extract from them useful, actionable intelligence to aid decision-making and other processes. This is true for a variety of industries, including semiconductor design, manufacturing, and test.

Moore’s Law (Figure 1) may be slowing with respect to traditional scaling of transistor critical dimensions. But as engineers continually develop ingenious ways to pack more functionality into a single product, e.g., 3D fabrication, multi-chip packaging, stacked die, and buried power rails (to name a few), the density of components in products is also increasing rapidly. Further driving this growth is an unprecedented increase in semiconductor demand, fueled by heightened online retailing, work-from-home scenarios, and transportation electrification.  

Figure 1. Illustration of Moore’s Law from 1970 to 2020.

One metric for tracking the overall semiconductor output is the number of transistors fabricated per year. VLSI Research [now part of TechInsights] has estimated that quantity for each decade since the inception of Moore’s Law, as shown in Figure 2, and estimates total output for 2021 was approximately 1.6×1021 (1.6 billion trillion) transistors!

Figure 2. Estimated number of transistors sold annually.

By even a highly conservative estimate, the test data resulting from this hard-to-imagine number of devices would be greater than 40 terabits per second! All that data must be analyzed – not only to determine which components are good and bad, but also for many other “bits” of intelligence: passing but “suspect” components, whether or not the product containing the components meets its datasheet and reliability requirements, whether or not the manufacturing and testing processes and equipment remain healthy and under control, and a host of other critical information.

Moreover, this estimate only addresses data generated by the test function and doesn’t include design, fab and test equipment, sensor, inspection, and calibration and maintenance data. So, we must deal with an ocean of data to streamline and optimize our production processes. It is a prime example of what Jack Morton from Bell Labs called the tyranny of numbers way back in 1958 [1].

Table 1 lists additional industry trends and associated test challenges that are changing today’s semiconductor test solution landscape.

Table 1. Industry trends and semiconductor test challenges.

Two facets of test significantly influenced by these trends are product quality and test cost.  New and subtle defect mechanisms, combined with the push toward ever higher levels of quality, increase the amount and complexity of testing and screening that must be performed to ensure low parts per billion test escape rates. All this testing, in turn, consumes more test time, thus increasing the cost of test. Semiconductor suppliers are looking largely to data analytics to solve these problems and keep the cost of test at reasonable levels without any compromise in outgoing quality or reliability. Let’s look at some examples of solutions Advantest is pursuing.

Dynamic parametric test

One of the earliest test steps performed on semiconductor devices is parametric test, also known as e-test or wafer acceptance test (WAT), which is performed during and following wafer manufacturing. The structures being tested can be individual transistors, resistors, and other components that are fabricated in the scribe lines, which are the small spaces between each die on a wafer, as illustrated in Figure 3 [2].  While these structures fill most of the scribe lines on the wafer, testing is typically limited to a few sites spread across the wafer surface.

Figure 3. Parametric testing involves structures fabricated in the wafer scribe lines between the die.

The test measurements provide valuable data used to monitor the health of the manufacturing process.  When anomalies are detected, typically the material flow is stopped so fab engineers can determine the cause of the problem. That often involves retesting material, collecting additional information, and performing additional manual analyses – all of which is disruptive and potentially costly to fab operations.

Dynamic parametric test (DPT) was created to automate and speed resolution of these types of excursions. Using DPT on an Advantest V93000/SMU8 parametric tester with PDF Solutions Exensio® software, a set of user-definable rules is established and checked during parametric testing. When the rules detect an issue, actions are immediately triggered to accelerate root-cause identification.

This process is illustrated in Figures 4 and 5. In this example, a diode measurement is being performed.  An out-of-specification measurement is detected, which triggers a DPT rule, and the test flow quickly adapts to a sweep of additional diode measurements across additional e-test sites on the wafer.  This real-time update collects the additional data necessary to diagnose the cause of the issue without requiring a stoppage of material flow and the reloading and retesting of aberrant wafers, thus saving both time and cost.  In the example cited here, the resulting root cause was quickly narrowed to a reticle or etch issue.

Figure 4. DPT detects out-of-spec diode parametric test.

Figure 5. DPT adaptively adjusts parametric test execution to collect additional data.

Production test edge computing

Downstream from parametric test is production testing. Wafer probe or wafer sort testing is performed while devices are still on the wafer. After good die have been singulated and packaged, they are subjected to final or package test. Other optional steps include system-level test, where die are subjected to a longer test that more closely resembles actual in-system operation, and burn-in, where the devices are tested, up to several hours, at elevated voltage and/or temperature to accelerate early life failures and measure product reliability.

Historically, production tests are a “one size fits all” proposition – for a given product, the same suite of tests is applied to every die. What’s desired, however, is to use data emerging from the test process itself to modify test content and execution so that each die sees the “right” tests. This process, which enables optimized deployment of test resources, is called adaptive test.

One form of adaptive test is executed as a post-test operation, e.g., wafer sort data is analyzed after the fact, and downstream final test operations are adjusted based on that analysis. However, semiconductor suppliers are also pursuing real-time adaptive test processes during production, in which test flow and content are altered during test execution, with low millisecond latencies. Several examples published in recent years describe scenarios that would work well when deployed as real-time adaptive test applications, including adaptive limit setting during search routines, predictive device trim, classifiers and device clustering, and burn-in optimization via at-risk device identification. [3] – [12]

Advantest developed ACS Edge to address this need for very fast, low-latency and highly secure analytics during production test. A high-performance compute platform with a dedicated, secure communication channel to the tester, ACS Edge wraps analytics in Docker containers to ensure reliable execution regardless of the compute environment’s configuration. All information related to the analytics and the data being analyzed is encrypted to prohibit unauthorized access that could compromise sensitive proprietary information.

Conclusion

As semiconductor product data sources become larger and more diverse, IC developers and manufacturers are challenged more than ever to deliver devices on time with highest quality and at the lowest possible cost. They are looking to advanced data analytics to extract intelligence needed to adjust manufacturing and test flows to adapt to an ever-changing environment. Test plays a pivotal role because it directly interfaces with each device to extract and analyze the data needed to monitor and control product quality and performance. DPT and test edge computing are just two approaches being deployed into production to address these challenges – we can expect to see more new solutions as innovation in manufacturing and test data analytics continues.

References

Trends in Testing: New Challenges Create New Opportunities

By Doug Lefever, Senior Executive Officer, Advantest Corporation, and President and CEO, Advantest America

As advancements in semiconductors and microelectronics soldier ahead into emerging, even uncharted, territory, new test challenges arise. To that end, let’s look at a few key trends and challenges that are driving opportunities for innovation in the test sector.

Technology convergence has been a buzzword for some time, and this trend is only going to intensify with the heightened need to move, access, and analyze massive volumes of data. As a result, data analytics technologies (Big Data, artificial intelligence [AI], and machine learning) will continue to play a vital role in driving test efficiencies – not just operational, e.g., improving overall equipment efficiency (OEE), but also transformational: enabling data to feed forward and backward between test insertions, as well as outside of test. The reality is that the lines are blurring between the front and back ends of test, and the insertion points change, depending on device type and lifecycle status. So, the test flows that happen throughout the lifecycle of the device need to be flexible.

Complex high-performance computing (HPC) and AI devices are growing very large, and because of interposers and bridging, their power requirements can exceed 1000W. This means that we need to be able to manage temperature with a high degree of precision during testing. These large devices also require additional compute and analytics capability during test. To this end, we developed our ACS Edge solution, which essentially adds a supercomputer alongside the tester to open up compute power and start to enable real-time adaptive test.

With these developments, the system will become enormously complex, requiring verification of entire systems (hardware, firmware/embedded applications, and software). This means we’ll be seeing a broader deployment of system-level testing (SLT) for both systems and modules, as well as SLT/ATE at the probe level for known good die, including active thermal management solutions. To this end, we’ve incorporated into our offerings the test-related accessories we acquired upon purchasing Essai, including sockets, thermal control units and other test subassemblies. Our value proposition rests in our ability to address the full hardware stack and in the comprehensive nature of our offerings.  

In the broader test arena, generation, validation, and optimization of required test content such as scan vectors, built-in self-test (BIST), and functional test (software code) will need massive support and cooperation between the EDA and ATE industries. Advantest has established strong relationships with the leading EDA providers to help drive these efforts. The industry is also going back and mixing functional tests more with structural tests, and more design-for-test (DFT) techniques are being added. While increased scan, serial high-speed scan over USB, and PCIe ports are being used, that still isn’t enough, which brings us back to SLT continuing to be deployed.

For 5G, test solutions are largely in place. Some high-volume manufacturing (HVM) device interfacing/interconnect technologies like over-the-air (OTA) are coming along, while test development is starting for advanced millimeter-wave (i.e., THz, 6G). There will also more use of on-chip sensors and agents to monitor device performance all the way through the fab, assembly and in-field. This traceability is vital to ensuring ATE plays a critical role in pulling data from sensors – this heightened need for data extraction and analysis is a recurring theme that permeates everything going forward.

Continued electrification of cars will also drive lots of growth in test, including challenging areas like high voltages – i.e., those greater than 1kV – which require different kinds of methodologies. These higher voltage requirements are also needed for silicon carbide (SiC) applications in vehicles. SiC, like gallium nitride (GaN), has been around for a long time and is finding new life in applications such as battery management. We can cover this with our mixed-signal configurations and our integrated power solutions.

With respect to packaging, we expect to see a bifurcation in the industry: HPC/AI will move to 2.5/3D ICs, while mobile will remain on monolithic 2D for a little while longer. We’re already into 2.5 and 3D, and we have been for some time. However, with hybrid bonding and die stacking, we’re moving into 3D IC. When that is fully implemented, it will bring some tough new challenges. We believe a holistic approach is required to create high-power solutions that will then be coupled with other chips in a package.

In addition, there will be new approaches to address the “memory wall,” such as large eRAMs, 3D stacked RAMs, co-packaging on 2.5D or access via serial I/O. Power consumption of I/Os may also drive the integration of optical I/O. The first step will be co-packaged optics (CPO), which involves heterogeneous integration of optics and silicon on a single packaged substrate aimed at addressing next-generation bandwidth and power challenges. 

As you can see, many technology trends have test requirements that overlap or coincide, with demands created by massive amounts of data generation and processing playing a massive role. Testing at the exascale level requires powerful equipment that can handle the challenge. We are meeting this challenge with our EXA Scale test system, built on our flagship V93000 architecture, which addresses the challenges of very high scan-data volumes, extreme power requirements, fast yield-learning and high-multisite configurations.